FLOPPY DISK SUBSYSTEM CONTROLLER

GM82C765B GM82C765B FLOPPY DISK SUBSYSTEM CONTROLLER General Description The GM82C765B is a CMOS LSI device which interfaces a host microprocessor to the floppy disk drive. It integrates the function of the Formatter/Controller, Data Separator. Write Precompensation, Data rate selection, Clock Generation, High Current Output Drivers, and TTL compatible Schmitt Trigger Receivers. The GM82C765B consists of a microprocessor interface, a microsequencer and a disk drive interface. The host microprocessor interface of the GM82C765B supports a 12MHz, 286 microprocessor bus without the use of wait states. All inputs within host microprocessor are Schmitt triggers, except for the data bus, XTAL, and the host output sink 12mA. Output drive capability is 20 LSTTL load, allowing direct interconnection to bus structures without the use of buffers or transceivers. On the disk drive interface, the GM82C765B includes data seperation that has been designed to address high performance error rate on floppy disk drives, and contains all the necessary logic to achieve classical 2nd order, type2, phase locked loop performance. Write precompensation is included, in addition to the usual formatting, encoding, decoding, step motor control, and status sensing functions For PC/XT and PC/AT applications, the device provides qualification of interrupt and DMA requests. The disk drive interface of the GM82C765B connects directly to up to four drives. All drive-related inputs are Schmitt triggers and the drive outputs are open drain, and sink 48 mA. The GM82C765B uses two clock inputs which provide the necessary signals for internal timing. A 16MHz oscillator controls the data rate of 500, 250 and 125Kbits/sec, while a 9.6MHz oscillator controls the 300Kbit/sec data rate used in PC/AT designs. The two XTAL oscillator circuits may be used for the 44-pin PLCC package, while TTL clock inputs must be provided when using the 40-pin DIP package. In the PLCC version of the GM82C765B pins 17 and 40, which were not utilized in DIP version of the GM82C765B, became DCHGEN (Disk Change Enable) and DCHG (Disk Change) respectively. Both are active LOW. DCHGEN is offered as an option for those designs that used the original GM82C765B part where DCHG did not exist as direct into the chip. The GM82C765B has eight internal Registers. The 8 bit main status register contains status information of the GM82C765B and may be accessed any time. Another four status register under system control also give various status and error information. The Control Register provides support logic that latches the two LSBs used to select the desired data rate that controls internal clock generation. The Operations Register replaces the standard latched port used in floppy subsystem. ∗ IBM PC compatible format (single and double density) – Floppy disk control and operations on chip – In PC AT mode, provides required signal qualification DMA channel – BIOS compatible and dual speed Spindle Drive support ∗ Integrates Formatter/Controller/Data Separation, Write Precompensation, Data rate Selection, Clock Generation, and drive interface Drivers and Receivers into one chip ∗ Multisector and Multitrack transfer capability. ∗ Direct Floppy Disk Drive interface with no buffers needed – 48mA sink output drivers – Schmitt trigger Line Receivers ∗ Enhanced Host Interface: – Supports 12MHz, 286 u-processor – Capable of driving 20 LSTTL Load ∗ Address mark detection circuitary internal to Floppy Disk Controller ∗ On chip Clock Generation Two TTL Clock Inputs for 40-DIP ∗ Two XTAL oscillator circuits for 44-Quad, PLCC ∗ User programmable Track Stepping Rate and Head load/unload time ∗ Drivers up to four Floppy or micro Floppy Disk Drives ∗ Data transfer DMA or non-DMA mode ∗ Parallel seek operations on up to four Drives ∗ Internal power up reset circuitry ∗ READ/WRITE access compatible register with 8 or 12MHz 286 microprocessor with 0 wait states. ∗ DMA timing corrected. ∗ LOW POWER CMOS, +5V SUPPLY Features 1 GM82C765B Pin Configuration RD WR CS AO DACK TC DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DMA IRQ LDOR LDCR RST RDD 1 2 3 4 5 6 7 8 9 10 GM82C765B 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC IDX TROO DS4., MO2 WP RPM, RWC HDL MO2. DS4 MO1, DS3 DS2 VSS DS1 STEP DIRC WD WE HS PCVAL CLK1 DRV CLK2 DBO DB1 HDL DS3., MO1 STEP VSS DS2 DIR 39 38 37 DCHG WP TROO IDX VCC RD WR CS A0 CACK TC 7 8 40 41 42 43 44 1 2 3 4 5 6 36 35 34 33 32 31 30 29 28 27 26 25 24 GM82C765B PL 23 22 21 20 19 18 HS PCVAL XT1 XT1 DRV XT2 XT2 RDD RST LDCR LDOR 9 10 11 12 13 14 15 16 17 DB2 DB4 DB3 DB6 DB5 DMA DB7 WD DCHGEN IRQ 1. Pin Descriptions PIN NO DIP PLCC 1 2 3 4 1 2 3 4 DACK MNEMOMIC RD WR CS SIGNAL NAME READ WRITE I/O I ST I ST I ST I ST FUNCTION Control Signal for transfer of data or status onto the data bus by the GM82C765B Control signal for latching data form the bus into the GM82C765B buffer register. Selected when 0 (Low) allowing RD or WR operation from the host Address line selecting data (=1) or status (=0) information (A0 = Logic 0 during WR is illegal) Used by the DMA Controller to transfer data from the GM82C765B onto the bus. Logical equivalent to CS and A0=1. In special or PC AT mode, this signal is qualified by DMAEN from the Operation Register. CHIP SELECT A0 ADDRESS LINE DMA ACKNOWLEDG E 5 5 (condinued on next page) 2 GM82C765B PIN DIP PLCC MENMO -MIC SIGNAL NAME I/O FUNCTION This signal indicates to GM82C765B that data transfer is complete. If DMA operational mode is selected for command execution, TC will be qualified by DACK , but not in the programmed I/O execution. In PC AT or Special mode, qualification by DACK requires the Operations mode, qualification by DACK requires the operations resister signal DMAEN to be logically true. Note also that in PC AT mode, TC will be qualified by DACK , whether in DMA or non-DMA host operation. programmed I/O in PC AT mode will cause an abnormal termination error at the completion of a command. 8-Bit bi-directional, tri-state, data bus. D0 is the least significant bit (LSB). D7 is the most significant bit (MSB) DMA request for byte transfer of data. In Special or PC AT mode, this pin is tristated, enabled by the DMAEN signal from the Operation Register. This pin is driven in the Base mode. Interrupt request indicating the completion of command execution or data transfer requests (in non DMA mode). Normally driven in base mode. In special or PC AT mode, this pin is tri-stated, enabled by the DMAEN signal from the Operations Resister. This input must be at logic = 0 to enable DCHG input status at pin 40 to be placed on DB7 during a RD = 0 of LDCR = 0. Internal pull-up. Address decode which enables the loading of the Operations Resister. Internally gated with WR creates the strobe which latches the two LSBS from the data bus into the Operation Resister. Address decode which enables the loading of the Control Resister. Internally gated with WR creates the strobe which latches the two LSRs from thedata bus into the Control Resister. Reset controller, placing microsequencer in idle. Resets device outputs. Puts in base mode, not PC AT or Special mode. This is the raw serial bit stream from the disk drive. Each falling edge of the pulses represents a flux transition of the encoded data. XTAL oscillator drive output for 44 pin PLCC should be left floating if TTL inputs used at pin 23. XTAL oscillator input used for non-standard data rates. It may be driven with a TTL level signal TTL level clock input used for non-standard data rates is 9.6MHz for 300 kbs, and can only be selected from the Control Register. * XT2 (PIN23) of 44 pin-PLCC 6 6 TC TERMINAL COUNT I ST 7-14 7-14 DBO thru DB7 DMA DATA BUS 0 Thru DATA BUS 7 DIRECT MEMORY ACCESS I/O BI O BI 15 15 16 16 IRQ INTERRUPT REQUEST O BI 17 DCHGEN DISK CHANGE ENABLE LOAD OPERATIONS REGISTER LOAD CINTROL REGISTER I ST I ST I ST I ST I ST O N I N I N 17 18 LDOR 18 19 LDCR 19 20 20 21 22 23 RST RESET READ DISK DATA XTAL 2 RDD XT 2 XT2 CLK2 XTAL2 CLOCK2 21 (condinued on next page) 3 GM82C765B Drive type input indicates to the device that a two-speed spindle motor is used if logic is O. In that case, the second clock input will never be selected and must be grounded. XTAL oscillator drive output for 44 pin PLCC should be left floating if TTL inputs used at pin 26. XTAL oscillator input requiring 16MHz crystal. This oscillator is used for all standard data rates, and may be driven with a TTL level signal. TTL level clock input is used to generate all internal timings for standard data rates. Frequency must be 16MHz ± 0.1%, and may 40/60 or 60/40 duty cycle. * XT1 (PIN 26) of 44-PLCC PRECOMPENSATION VALUE select input. This pin determines the amount of write precompensation used on the inner tracks of the diskette. Logic 1 = 125nS, Logic 0 = 187nS High Current drive (HCD) output selects the head (side) of the floppy disk that is being read or written. Logic 1 = side 0. Logic 0 = side 1. This HCD output becomes true, active low, just prior to writing on the diskette. This allows current to flow through the write head. This HCD output WRITE DATA . Each failing edge of the encoded data pulse stream causes a flux transition on the media. This HCD output determines the direction of the HEAD step motor. Logic 1 = outward motion. Logic 0 = inward motion. This HCD output issues an active low pulse for each track to track movement of the head. This 30 33 DS1 22 24 DRV DRIVE TYPE I ST O ST I N I N 25 26 XI1 XTAL1 XT1 XTAL1 23 CLK1 CLOCK1 24 27 PCVAL PRECOMPEN-SATION VALUE HEAD SELECT I ST O HCD O HCD O HCD O HCD O HCD 25 28 HS 26 29 WE WRITE ENABLE 27 30 WD WRITE DATA 28 31 DIRC DIRECTION 29 32 STEP PULSE STEP CONTROL DRIVE SELECT1 O HCD 31 34 VSS GROUND 32 35 DS2 DRIVE SELECT2 O HCD 33 36 MO1 , DS3 MOTOR ON 1 DRIVE