(GD16584 / GD16588) Receiver / CDR and DeMUX

www.DataSheet4U.com an Intel company 10 Gbit/s Receiver, CDR and DeMUX GD16584/GD16588 (FEC) Preliminary General Description GD16584 and GD16588 are Receiver chips for use in STM-64/192 and Optical Transport Networking (OTN) systems. The component is available in two versions: u GD16584 for 9.5328 Gbit/s. u GD16588 for 10.66 Gbit/s for OTN or Forward Error Correction (FEC). Except the different operating bit rates the two versions are functional identical. The receiver is a Clock and Data Recovery IC with: u a low noise VCO u a Bang-Bang Phase Detector u a 1:16 De-multiplexer u a Lock Detect u a Phase and Frequency Detector. Clock and data are regenerated by using a Phase Locked Loop (PLL) with an external passive loop filter. The VCO frequency is controlled by one of the two Phase Detectors in order to ensure capture and lock to the line data rate. The Lock Detector circuit monitors the VCO frequency and determines when the VCO is within the lock range. When the frequency deviates more than VCO VCTL Timing Control Features 500 ppm from the reference clock, it automatically switches the phase and frequency detector into the PLL loop. In the auto lock mode the locking range is selectable between 500 or 2000 ppm. When the VCO frequency is within the lock range, the Bang-Bang Phase Detector takes over. It controls the phase of the VCO until the sampling point of data is in the middle of the bit period, where the eye opening is largest. A ±40 mV Decision Threshold Control (DTC) is provided at the 10 Gbit/s input. The 10 Gbit/s input data is sampled and de-multiplexed by the 1:16 DeMUX. The parallel output interface is synchronised with the 622 MHz output clock. The clock and data outputs are LVDS compatible. The device operates from a dual -5.2 V and +3.3 V power supply. The power dissipation is 3.3 W, typical. The device is manufactured in a Silicon Bipolar process and packaged in an 132 ball 13 × 13 mm Ceramic/Plastic Ball Grid Array (BGA). CKOUT CKOUTN l Complete Clock and Data Recovery IC with auto acquisition. 1:16 DeMUX with differential 622 Mbit/s data outputs 622 MHz Clock output. LVDS compatible clock and data outputs. OIF99.102.5 compliant timing. 155 or 622 MHz Reference Clock. Input Decision Threshold Control (DTC): ±40 mV. Low noise VCO with ±5 % tuning range. Dual supply operation: -5.2 V and +3.3 V. Power dissipation: 3.3 W (typ). Silicon Bipolar technology. Available in three package versions: – EB: 132 ball (16 mill) Ceramic BGA 13 × 13 mm – EF: 132 ball (20 mill) Ceramic BGA 13 × 13 mm – FB: 132 ball (20 mill) Plastic BGA 13 × 13 mm Available in two versions: – GD16584 for 10 Gbit/s – GD16588 for 10.66 Gbit/s l l l l l l l l l l l DO0 DON0 DI DIN l DTC DTCN Decision Threshold Control Bang Bang Phase Detector 1:16 Demultiplexer Parallel Output Data DO15 DON15 U REFCK REFCKN Phase Frequency Detector 1/4 D PCTL Applications l (PHIGH) (PLOW) Lock Detect LOCK l Telecommunication systems: – SDH STM-64 – SONET OC-192. – Optical Transport Networking (OTN) – FEC applications Fibre optic test equipment. Submarine systems. Data Sheet Rev.: 12 RESET TCK SEL3 SEL1 SEL2 VCC VDD VDDA VDDO VEE VEEA l www.DataSheet4U.com Functional Details The application of GD16584 is as receiver in SDH STM-64 and SONET OC-192 optical communication systems. It integrates: u a Voltage Controlled Oscillator (VCO) u a Bang Bang Phase Detector u a Lock Detect Circuit u a 1:16 DeMUX u a Phase and Frequency Detector (PFD). Loop Filter A passive loop filter is used for the CMU consisting of a resistor and a capacitor driven from the PCTL pin. The PCTL pin outputs the phase information from the Bang-Bang Phase Detector. The phase information is very high frequency pulses (200 ps pulse width) either charging or discharging the external capacitor. The values of the external components determines the characterisctics of the PLL, e.g. bandwidth and transfer functions. For recommended loop filter values, please refer to Figure 1. The PCB lay-out of the external loop filter and the connecting lines between PCTL and VCTL are critical for jitter performance of the device. The external components and the artwork should be placed very close to the pins of the device. If the PHIGH and PLOW outputs are not used they must be shorted VDD (0 V), please refer to Figure 1. and DIN) whereby the DC bias voltage at the input is adjustable by ±40 mV. Optimizing the input decision threshold improves the system input sensitivity by 1-2 dB typical. The input impedance into DTC and DTCN is 1.5 kW and when not used they should be de-coupled to 0 V by 100 nF. The select inputs (SEL1-3, RESET and TCK) are low speed inputs that can be connected directly to the supply rails (0 / -5.2 V). The 10 Gbit/s inputs (DI and DIN) are not ESD protected and extra precautions are needed when handling these inputs. (Internal 50 W resistors provide some ESD hardness making the input low impendance.) VCO The VCO is an LC-type differential oscillator, voltage controlled by pin VCTL and with a tuning range of approximately ±5 %. For GD16584, with the VCTL voltage at approximately -3.5 V, the VCO frequency is fixed at 9.953 GHz and by changing the voltage from 0 to -5.2 V the frequency is controlled from 8.9 GHz to 10.2 GHz. The modulation bandwidth of VCTL is 90 MHz. Bit Order The serial data stream is demultiplexed with the first received bit on DO0, the second on DO1 and with last received bit in a 16 bit frame on DO15. The naming is opposite to the OIF99.102.5 recommendation. For OIF interfaces the data pins should be connected as shown in the following table. Note: The clock output is inverted in order to refer the data crossing to the rising edge of CKOUTN OIF: RXDATA15_P/N (MSB) RXDATA14_P/N RXDATA13_P/N RXDATA12_P/N RXDATA11_P/N RXDATA10_P/N RXDATA9_P/N RXDATA8_P/N RXDATA7_P/N RXDATA6_P/N RXDATA5_P/N RXDATA4_P/N RXDATA3_P/N RXDATA2_P/N RXDATA1_P/N PFD The PFD ensures predictable locking conditions for the device. It is used during acquisition and pulls the VCO into the locking range where the Bang-Bang Phase Detector acquires lock to the incoming bit-stream. The PFD is made with digital set/reset cells giving it a true phase and frequency characteristic. The reference clock input (REFCK/REFCKN) to the PFD is differential and selectable between 155 MHz or 622 MHz by SEL3. The reference clock is a CML input with 50 W internal termination resistors to 0 V. The reference clock is typically an X-tal oscillator type as shown in Figure 1. The reference clock input should be used differential for best performance. If the reference clock is DC coupled the input voltage swing is 0 V (high) and -0.4 V (low). Lock Detect Circuit The lock detect circuit continuously monitors the difference between the reference clock and the VCO clock. If they differ by more than 500 ppm (or 2000 ppm), it switches the PFD into the PLL, to pull it back into the locking range. The status of the lock circuit is given by output pin (LOCK). Manual or automatic lock is selected by SEL1. In auto lock mode, the lock range ±500 or ±2000 ppm is selected by SEL2. The LOCK output is an open collector output, and should be terminated with an external resistor. The maximum termination voltage is +3.5 V. Output Pin: DO0/DON0 DO1/DON1 DO2/DON2 DO3/DON3 DO4/DON4 DO5/DON5 DO6/DON6 DO7/DON7 DO8/DON8 DO9/DON9 DO10/DON10 DO11/DON11 DO12/DON12 DO13/DON13 DO14/DON14 The Inputs The input amplifier pin (DI/DIN) is designed as a gain buffer stage with high sensitivity and internal 50 W resistors terminated to 0 V. After retiming, the data is de-multiplexed down to 16 bit/s by demultiplexer. It is recommended to use the 10 Gbit/s inputs differentially for best input sensitivity. The input voltage decision threshold is adjustable by pin DTC and DTCN when connected to a potentiometer. Adjusting the resistor value of the meter controls the current into DTC and DTCN. This DC current is mirrored to the input pin (DI Bang-Bang Phase Detector The Bang-Bang phase detector is designed as a true digital type producing a binary output. It samples the incoming data prior to, in the vicinity of and after any potential bit transition. When a transition has occurred, these three samples tell whether the VCO clock leads or lags the data. The binary output is filtered through the (low pass) loop filter, performing an integration of all potential bit transitions. Hence the PLL is controlled by the bit transition point. Data Sheet Rev.: 12 GD16584/GD16588 Page 2 of 15 Output Pin: www.DataSheet4U.com DO15/DON15 CKOUT CKOUTN OIF: RXDATA0_P/N (LSB) RXCLK_N RXCLK_P Thermal Condition The device dissipates 3.3 W from a dual voltage supply (–5.2 V and +3.3 V). The power consumption from the -5.2 V supply is approximately 2.9 W and 0.4 W from the +3.3 V supply. The die is mounted on a metal pad directly connected to the center balls (E4-9, F4-9, G4-9, and H4-9). It is important to have a good thermal connection from the center balls of the package via the PCB to the ambient environment to ensure the best thermal conditions. Note: To obtain TCASE < 70°C, the PGBA requires (compared to the CBGA) additional cooling on the case. For details, please refer to Application Note “ PBGA Thermal data....”. The Outputs The data and clock outputs are LVDS compatible outputs with internal bias resistors (500 W) to VCC (+3.3 V) Refer to item “LVDS Compatible Interface” on page 6. Timing to System ASIC The timing between GD16584 and the system ASIC at 622 Mbit/s is controlled by the 622 MHz output clock synchronized with the output data. The clock is used as the input clock to the ASIC, clocking the input data into 16 parallel registers. The timing relation between the clock and data is given by the AC Characteristics. For a OIF99.102.5 complaint timing the output clock should be inverted by using: u CKOUTN as the positive output clock (RXCLK_P), and u CKOUT as the negat