Description
Ne Tolew 5V Inp rant u 16L ts on V8D Features • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology • 3.3V LOW VOLTAGE 16V8 ARCHITECTURE — JEDEC-Compatible 3.3V Interface Standard — 5V Compatible Inputs — I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C) • ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only) • E CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention • EIGHT OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity • PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability • APPLICATIONS INCLUDE: — Glue Logic for 3.3V Systems — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade • ELECTRONIC SIGNATURE FOR IDENTIFICATION 2 GAL16LV8 Low Voltage E2CMOS PLD Generic Array Logic™ Functional Block Diagram I/CLK CLK 8 I 8 I OLMC I/O/Q OLMC I/O/Q PROGRAMMABLE AND-ARRAY (64 X 32) 8 OLMC I/O/Q I 8 OLMC I/O/Q I 8 OLMC I/O/Q I 8 OLMC I/O/Q I 8 I 8 I OLMC OE OLMC I/O/Q I/O/Q I/OE Description The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5V signal levels. The GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and supports all architectural features such as combinatorial or registered macrocell operations. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Pin Configuration PLCC I I 2 I I I I I 8 14 9 I GND 11 I/OE I/O/Q 13 I/O/Q 6 4 I/CLK Vcc 20 18 I/O/Q I/O/Q I/O/Q GAL16LV8 Top View 16 I/O/Q I/O/Q I/O/Q Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com December 1997 16lv8_04 1 Specifications GAL16LV8 GAL16LV8 Ordering Information Commercial Grade Specifications Tpd (ns) 3.5 5 7.5 10 15 Tsu (ns) 3 4 6 7 12 Tco (ns) 2.5 3 5 7 10 Icc (mA) 70 70 65 65 65 Ordering # GAL16LV8D-3LJ GAL16LV8D-5LJ GAL16LV8C-7LJ GAL16LV8C-10LJ GAL16LV8C-15LJ Package 20-Lead PLCC 20-Lead PLCC 20-Lead PLCC 20-Lead PLCC 20-Lead PLCC Part Number Description XXXXXXXX _ XX X X X GAL16LV8D Device Name GAL16LV8C Speed (ns) L = Low Power Power Grade Blank = Commercial Package J = PLCC 2 Specifications GAL16LV8 Output Logic Macrocell (OLMC) The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes are illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL16LV8. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. The following is a list of the PAL architectures that the GAL16LV8 can emulate. It also shows the OLMC mode under which the GAL16LV8 emulates the PAL architecture. PAL Architectures Emulated by GAL16LV8 16R8 16R6 16R4 16RP8 16RP6 16RP4 16L8 16H8 16P8 10L8 12L6 14L4 16L2 10H8 12H6 14H4 16H2 10P8 12P6 14P4 16P2 GAL16LV8 Global OLMC Mode Registered Registered Registered Registered Registered Registered Complex Complex Complex Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Compiler Support for OLMC Software compilers support the three different global OLMC modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types listed in the table can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1 and pin 11 are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins ( pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output. Registered ABEL CUPL LOG/iC OrCAD-PLD PLDesigner TANGO-PLD P16V8R G16V8MS GAL16V8_R "Registered"1 P16V8R2 G16V8R Complex P16V8C G16V8MA GAL16V8_C7 "Complex"1 P16V8C2 G16V8C Simple P16V8AS G16V8AS GAL16V8_C8 "Simple"1 P16V8C2 G16V8AS3 Auto Mode Select P16V8 G16V8 GAL16V8 GAL16V8A P16V8A G16V8 1) Used with Configuration keyword. 2) Prior to Version 2.0 support. 3) Supported on Version 1.20 or later. 3 Specifications GAL16LV8 Registered Mode In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture configurations available in this mode are similar to the common 16R8 and 16RP4 devices with various permutations of polarity, I/O and register placement. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or I/ O. Up to eight registers or up to eight I/Os are possible in this mode. Dedicated input or output functions can be implemented as subsets of the I/O function. Registered outputs have eight product terms per output. I/Os have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page. CLK Registered Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - Pin 1 controls common CLK for the registered outputs. - Pin 11 controls common OE for the registered outputs. - Pin 1 & Pin 11 are permanently configured as CLK & OE for registered output configuration. D Q Q XOR OE Combinatorial Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this output configuration. - Pin 1 & Pin 11 are permanently configured as CLK & OE for registered output configuration. XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 4 Specifications GAL16LV8 Registered Mode Logic Diagram PLCC Package Pinout 1 0 4 8 12 16 20 24 28 2128 PTD 0000 OLMC 0224 19 2 0256 XOR-2048 AC1-2120 OLMC 0480 18 3 0512 XOR-2049 AC1-2121 OLMC 0736 17 4 0768 XOR-2050 AC1-2122 OLMC 0992 16 5 1024 XOR-2051 AC1-2123 OLMC 1248 15 6 1280 XOR-2052 AC1-2124 OLMC 1504 14 7 1536 XOR-2053 AC1-2125 OLMC 1760 13 8 1792 XOR-2054 AC1-2126 OLMC 2016 12 9 2191 XOR-2055 AC1-2127 OE 11 SYN-2192 AC0-2193 5 Specifications GAL16LV8 Complex Mode In the Complex mode, macrocells are configured as output only or I/O functions. Architecture configurations available in this mode are similar to the common 16L8 and 16P8 devices with programmable polarity in each macrocell. Up to six I/Os are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer most macrocells (pins 12 & 19) do not have input capability. Designs requiring eight I/Os can be implemented in the Registered mode. All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 1 and 11 are always available as data inputs into the AND array. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Combinatorial I/O Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active L

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