Low Power Phase-locked Loop IC

www.DataSheet4U.com FS8170 2.5 GHz Low Power Phase-locked Loop IC HiMARK Technology, Inc. reserves the right to change the product described in this datasheet. All information contained in this datasheet is subject to change without prior notice. HiMARK Technology, Inc. assumes no responsibility for the use of any circuits shown in this datasheet. Description The FS8170 IC is a serial data input, fully programmable phase-locked loop with a 2.5 GHz prescaler for use in the local oscillator subsystem of radio transceivers. Multi-modulus division ratios of 32/33 and 64/65 are selectable thru serial programming to enable pulse swallowing operation. When combined with an external VCO, the FS8170 becomes the core of a very low power frequency synthesizer well-suited for mobile communication applications, such as 2.4 GHz ISM-band wireless data links and cellular GSM and PCS. The FS8170 is also pin compatible with Fujitsu’s MB15E07SL IC. Features ! ! ! ! ! ! ! ! ! Maximum input frequency: 2.5 GHz Supply voltage range from 2.4 V to 3.6 V Low current consumption in locked state: 3.5 mA typ. (VCC = VP = 2.7 V, TA = +25 °C) 4.0 mA typ. (VCC = VP = 3.0 V, TA= +25 °C) 10 µA max. in asynchronous power-down mode Digitally-filtered lock detect output 18-bit programmable input frequency divider using ÷ 32/33/64/65 multi-modulus prescaler with divide ratio range from 992 to 65631 for ÷ 32/33 mode and from 4032 to 131135 for ÷ 64/65 mode 14-bit programmable reference frequency divider with divide ratio range from 3 to 16383 Programmable charge pump current: 1.5 mA or 6 mA Pin compatible with Fujitsu MB15E07, MB15E07L, MB15E07SL 16 pin, plastic TSSOP (0.65 mm pitch) Package and Pin Assignment 16 pin, plastic TSSOP (dimensions in mm) XIN XOUT VP VCC DO VSS XFIN FIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 φR φP FOLD ZC EN LE DATA CLK HiMARK FS8170 Page 1 May 2003 FS8170 Pin Descriptions Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name XIN XOUT VP VCC DO VSS XFIN FIN CLK DATA LE EN ZC FOLD φP φR I/O I O — — O — I I I I I I I O O O Description Reference crystal oscillator or external clock input with internally biased amplifier Reference crystal oscillator output Power supply voltage for the charge pump Power supply voltage Single-ended charge pump output Ground Complementary input for prescaler (normally ac-bypassed via a capacitor) VCO frequency input with internally biased input amplifier Shift register clock input Serial data input Load enable signal input Power-down control Forced high-impedance control for the charge pump Multiplexed CMOS level output (see Functional Description section for programming information) Phase comparator N-channel open drain output for an external charge pump Phase comparator CMOS inverter output for an external charge pump Functional Block Diagram FIN XFIN N-PRESCALER N-COUNTER φR φP N-LATCH DATA CLK LE EN CONTROL LOGIC SHIFT REGISTER PFD CHARGE PUMP DO ZC R-LATCH LOCK DETECTOR LD MUX FOLD XIN XOUT OSC R-COUNTER Page 2 May 2003 FS8170 Absolute Maximum Ratings VSS = 0 V Parameter Symbol VCC Supply voltage range VP Input voltage range Output voltage range VDO Storage temperature range Soldering temperature range Soldering time range ESD rating (human body mode) TSTG TSLD tSLD VSS to VP –55 to 125 260 4 3500 V °C °C s eV VFIN VO VCC to 6.0 VSS – 0.5 to VDD + 0.5 VSS to VCC V V V Rating VSS – 0.3 to VSS + 4.0 Unit V Recommended Operating Conditions VSS = 0 V Value Parameter Symbol min. VCC Supply voltage range VP Operating temperature TA Vcc –40 – 25 5.5 80 V °C 2.4 typ. 3.0 max. 3.6 V Unit Page 3 May 2003 FS8170 Electrical Characteristics (VCC = VP = 3.0 V, VSS = 0 V, TA = –40 to 85 °C unless otherwise noted) Value Parameter Symbol Condition min. typ. max. Unit GENERAL Power supply current consumption Standby current consumption FIN operating frequency XIN operating frequency Input sensitivity XIN input voltage swing ICC,total ICC,standby fFIN fXIN PFIN VXIN 50 Ω measurement system fin = 2.5 GHz ZC = “H” or open VFIN = 0.3 Vpk-pk sinusoid 50 3 -15 0.5 4 10 2500 40 +2 VCC mA µA MHz MHz dBm Vpk-pk CHARGE PUMP IDOsource IDOsink RF charge pump output current IDOsource IDOsink VDO = VP/2, CS bit = “L” VDO = VP/2, CS bit = “L” -1.5 1.5 mA mA VDO = VP/2, CS bit = “H” VDO = VP/2, CS bit = “H” -6 6 mA mA DIGITAL INTERFACE (DATA, CLK, LE, PS, ZC) High-level input voltage Low-level input voltage High-level input current Low-level input current XIN logic HIGH input current XIN logic LOW input current φP logic LOW output voltage φP logic LOW output current φR logic HIGH output voltage φR logic LOW output voltage φR logic HIGH output current φR logic LOW output current VIH VIL IIH IIL IIH,XIN IIL,XIN VOL IOL VOH VOL IOH IOL VIH = VCC = 3.6V VIL = 0 V, VCC = 3.6V VIH = VDD VIL = 0 V Open drain output Open drain output VCC = VP = 3.0 V, IOH = –1 mA VCC = VP = 3.0 V, IOL = 1 mA VCC = VP = 3.0 V VCC = VP = 3.0 V 1 1 VCC – 0.4 0.4 –1 –100 0.4 –1 –1 0.8×VCC 0.2×VCC V V µA µA µA µA V mA V V mA mA 1 1 100 Page 4 May 2003 FS8170 Electrical Characteristics (VCC = VP = 3.0 V, VSS = 0 V, TA = –40 to 85 °C unless otherwise noted) Value Parameter Symbol Condition min. FOLD logic HIGH output voltage FOLD logic LOW output voltage FOLD logic HIGH output current FOLD logic LOW output current VOH VOL VOH VOL VCC = VP = 3.0 V, IOH = –1 mA VCC = VP = 3.0 V, IOL = 1 mA VCC = VP = 3.0 V VCC = VP = 3.0 V 1 VCC – 0.4 0.4 –1 typ. max. V V mA mA Unit MICROWIRE TIMING DATA to CLK setup time DATA to CLK hold time CLK to LE setup time CLK to LE hold time LE Pulse width tSU1 tHOLD1 tSU2 tHOLD2 tEW 10 10 20 30 50 ns ns ns ns ns Page 5 May 2003 FS8170 Functional Description Programmable Input Frequency Divider The VCO output to the FIN pin is divided by the programmable divider and then internally output to the phase/frequency detector (PFD) as fV. The programmable input frequency divider consists of a multi-modulus (selectable ÷ 32/33 or ÷ 64/65 (M/M+1)) prescaler and a 18-bit N-counter, which is further comprised of a 7-bit swallow A-counter, and a 11-bit main B-counter. The total divide ratio, N, is related to values for M, A, and B through the relation N = ( M + 1 ) × A + M × ( B – A ) = M × B + A, with B ≥ A. The minimum programmable divisor for continuous counting is given by M × ( M – 1 ) , and is 32 × ( 32 – 1 ) = 992 for the ÷ 32/33 prescaler mode, and is 64 × ( 64 – 1 ) = 4032 for the ÷ 64/65 mode. Hence, the valid total divide ratio range for the input divider is N = 992 to 65631 for the ÷ 32/33 mode and N = 4032 to 131135 for the ÷ 64/65 mode. Programmable Reference Frequency Divider The crystal oscillator output is divided by the programmable reference divider and then internally output to the PFD as fR. The programmable reference frequency divider consists of a 14-bit reference R-counter. Becasue of its specific design, the minimum acceptable divisor for R is 3, and hence the total divide ratio, R, ranges from 3 to 16383. Shift Register Configuration The divide ratios for the input and reference dividers are input using a 19-bit serial interface consisting of separate clock (CLK), data (DATA), and load enable (LE) lines. The format of the serial data is shown in Table 1. The data on the DATA line is written to the shift register on the rising edge of the CLK signal and is input with MSB first, and the last bit is used as the latch select control bit. The data on the DATA line should be changed on the falling edge of CLK, and LE should be held LOW while data is being written to the shift register. Data is transferred from the shift register to one of the frequency divider latches when LE is set HIGH. When the latch select control bit is set LOW, data is loaded to the 18-bit N-counter latch, and when the latch select control bit is set HIGH, the 4 MSBs are recognized as CS, LDS, FC, SW, respectively, and the next 14 data bits are loaded to the 14-bit R-counter latch. The definition of the 4 MSBs will be described in Table 5 and 6. Note that LDS should be set LOW for normal operation. Also, serial input data timing waveforms are shown in Fig. 1. Page 6 May 2003 FS8170 Fig. 1 – Serial data input waveforms DATA tSU1 tSU2 tHOLD1 CLK LE CONTROL BIT 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DATA CLK LE MSB 1 Parameter tSU1 tSU2 tHOLD1 Min. 10 20 10 Typ. – – – Max. – – – Unit ns ns ns LSB Data Flow MSB Table 1: Serial data input format 1 2 A 1 R 1 3 A 2 R 2 4 A 3 R 3 5 A 4 R 4 6 A 5 R 5 7 A 6 R 6 8 A 7 R 7 9 N 1 R 8 10 N 2 R 9 11 N 3 R 10 12 N 4 R 11 13 N 5 R 12 14 N 6 R 13 15 N 7 R 14 16 N 8 S W 17 N 9 F C 18 N 10 L D S 19 N 11 C S C B CB A1 to A7 B1 to B11 R1 to R14 SW FC LDS CS Control bit for selecting the N or R latch Control bits for setting the divide ratio of the programmable swallow counter (0 to 127) Control bits for setting the divide ratio of the programmable main counter (3 to 2047) Control bits for setting the divide ratio of the programmable reference counter (3 to 16383) Control bit for setting the divide ratio of the prescaler (32/33 or 64/65) Control bit for setting the polarity of the phase/frequency detector Control bit for selecting the output for the FOLD pin Control bit for setting the charge pump current level Page 7 May 2003 FS8170 Table 2: Binary 7-bit data format for swallow counter Divide ratio (A) 0 1 . 127 A 7 0 0 . 1 A 6 0 0 . 1 A 5 0 0 . 1 A 4 0 0 . 1 A 3 0 0 . 1 A 2 0 0 . 1 A 1 0 1 . 1 Table 3: Binary 11-bit data format for main counter Divide ratio (B) 3 4 . 2047 N 11 0 0 . 1 N 10 0 0 . 1 N 9 0 0 . 1 N 8 0 0 . 1 N 7 0 0 . 1 N 6 0 0 . 1 N 5 0 0 . 1 N 4 0 0 . 1 N 3 0 1 . 1 N 2 1 0 . 1 N 1 1 0 . 1 Table 4: Binary 14-bit data format for reference counter Divide ratio (R) 3 4 . 16383 R 14 0 0 . 1 R 13 0 0 . 1 R 12 0 0 . 1 R 11 0 0 . 1 R 10 0 0 . 1 R 9 0 0 . 1 R 8 0 0 . 1 R 7 0 0 . 1 R 6 0 0 . 1 R 5 0 0 . 1 R