Dual Phase-locked Loop IC

www.DataSheet4U.com FS8160 1.1 GHz/1.1 GHz Dual Phase-locked Loop IC HiMARK Technology, Inc. reserves the right to change the product described in this datasheet. All information contained in this datasheet is subject to change without prior notice. HiMARK Technology, Inc. assumes no responsibility for the use of any circuits shown in this datasheet. Description The FS8160 is a serial data input, fully programmable dual phase-locked loop IC for use in the local oscillator subsystem of radio transceivers. When combined with external VCOs, the FS8160 becomes the core of a very low power dual frequency synthesizer wellsuited for mobile communication applications. The FS8160 is pin-compatible with National Semiconductor’s LMX1602 IC. Features Supply voltage operating range: 2.7 to 3.6 V Maximum input frequency: 1.1 GHz/1.1 GHz (main/auxiliary) Low current consumption (IDD,total typically 5 mA at VDD,main = VDD,aux = 3.0 V and < 1 µA in power down mode) 16-bit programmable input (both main and auxiliary) frequency dividers (including a ÷ 16/17 prescaler) with divide ratio range from 240 to 65535 12-bit programmable reference (both main and auxiliary) frequency dividers with divide ratio range from 2 to 4095 Programmable charge pump output Digital-filtered lock detect output 16 pin, plastic TSSOP (0.65 mm pitch) Package and Pin Assignment 16 pin, plastic TSSOP (dimensions in mm) FOLD XIN XOUT VSSA FINA VDDA DOA ENA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLK DATA LE VSSM FINM VDDM DOM ENM HiMARK FS8160 Page 1 April 2003 FS8160 Pin Descriptions Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name FOLD XIN XOUT VSSA FINA VDDA DOA ENA ENM DOM VDDM FINM VSSM LE DATA CLK I/O O I O — I — O I I O — I — I I I Description Multiplexed CMOS level output (see Programming Description section) Reference crystal oscillator or external clock input with internally biased amplifier Reference crystal oscillator output used with external resonator Ground (aux PLL) VCO frequency input with internally biased input amplifier (aux PLL) Nominal 3.0 V supply voltage (aux PLL) Single-ended charge pump output (aux PLL) Enable control input; normal operation when high, power-down mode when low (aux PLL) Enable control input; normal operation when high, power-down mode when low (main PLL) Single-ended charge pump output (main PLL) Nominal 3.0 V supply voltage (main PLL) VCO frequency input with internally biased input amplifier (main PLL) Ground (main PLL) Latch enable input Serial data input Shift register clock input Functional Block Diagram FINM XIN XOUT DATA CLK LE ENM ENA MAIN PRESCALER N-COUNTER PFD R-COUNTER MAIN LATCH LOCK DETECTOR FOLD MUX LOCK DETECTOR CHARGE PUMP DOM OSC CONTROL LOGIC SHIFT REGISTER FOLD AUX LATCH R-COUNTER FINA AUX PRESCALER PFD N-COUNTER CHARGE PUMP DOA Page 2 April 2003 FS8160 Absolute Maximum Ratings VSS = 0 V Parameter Supply voltage Symbol VDD,main VDD,aux VFIN,main VFIN,aux TOPR TSTG TSLD tSLD Rating VSS – 0.3 to VSS + 6.5 VSS – 0.3 to VSS + 6.5 VSS – 0.3 to VDD,main + 0.3 VSS – 0.3 to VDD,aux + 0.3 –40 to 85 –40 to 125 255 10 Unit V V V V °C °C °C s Input voltage range Operating temperature range Storage temperature range Soldering temperature range Soldering time range Recommended Operating Conditions VSS = 0 V Value Parameter Symbol min. VDD,main Supply voltage range VDD,aux Operating temperature TA VDD,main –40 25 VDD,main 85 V °C 2.7 typ. max. 3.6 V Unit Page 3 April 2003 FS8160 Electrical Characteristics (VDD,main = VDD,aux = VDD = 3.0 V, TA = 25 °C unless otherwise noted) Value Parameter Symbol Condition min. GENERAL Current consumption Standby current consumption FIN operating frequency range IDD,total IDD,standby fFIN 1.1 GHz + 1.1 GHz 1.1 GHz only ENM = ENA = low Main Auxiliary Logic mode Crystal mode Main Auxiliary 100 100 1 1 –15 –15 0.5 5.0 2.5 1 1100 1100 40 20 0 0 VDD,aux Unit typ. max. mA mA µA MHz MHz MHz MHz dBm dBm Vpk-pk XIN operating frequency range fXIN FIN input sensitivity XIN input sensitivity DIGITAL INTERFACE Logic LOW input voltage Logic HIGH input voltage Logic LOW input current Logic HIGH input current XIN logic LOW input current XIN logic HIGH input current PFIN VXIN VIL VIH IIL IIH IIL,XIN IIH,XIN VIL = 0 V, VDD = 3.6 V VIH = VDD = 3.6 V VIL = 0 V, VDD = 3.6 V VIH = VDD = 3.6 V Logic mode, VXOUT = VDD/2, VDD = 3.6 V Crystal mode, VXOUT = VDD/2, VDD = 2.7 V IOL = 500 µA IOH = –500 µA VDD – 0.4 |300| 0.8 × VDD –1 –1 –100 0.2 × VDD V V 1 1 µA µA µA 100 |200| µA µA µA XOUT output current magnitude IXOUT Logic LOW output voltage Logic HIGH output voltage SERIAL PROGRAMMING TIMING DATA to CLK setup time DATA to CLK hold time VOL VOH 0.4 V V tSU1 tH1 50 10 nS nS Page 4 April 2003 FS8160 Electrical Characteristics (continued) (VDD,main = VDD,aux = VDD = 3.0 V, TA = 25 °C unless otherwise noted) Value Parameter Symbol Condition min. CLK to LE setup time CLK pulse width logic HIGH CLK pulse width logic LOW LE pulse width CHARGE PUMP High gain mode, VDOM,VDOA = VDD/2 Low gain mode, VDOM,VDOA = VDD/2 High gain mode, VDOM,VDOA = VDD/2 Low gain mode, VDOM,VDOA = VDD/2 0.5 V ≤ V DOM ,VDOA ≤ V DD – 0.5 V Unit typ. max. nS nS nS nS tSU2 tPWH tPWL tPW 50 50 50 50 –1600 µA µA µA µA nA IDO,source Charge pump output current IDO,sink –160 +1600 +160 1 Charge pump high-Z state current IDO,high-Z Page 5 April 2003 FS8160 Functional Description The FS8160 dual phase-locked loop (PLL) IC contains two identical PLLs (main and auxiliary). Both the main and auxiliary PLLs share the crystal oscillator, serial data input logic, and multi-function lock detector output circuits. Each PLL has its own programmable input and reference frequency dividers, phase/frequency detectors, programmable charge pumps, and digital-filtered lock detectors. Programmable Input Frequency Divider The VCO input to the FIN pin is divided by the programmable divider and then internally output to the phase/frequency detector (PFD) as fV. The programmable input frequency divider consists of a ÷ 16/17 (P/P+1) dual-modulus prescaler and a 16-bit (N) counter, which is further comprised of a 4-bit swallow (A) counter, and a 12-bit main (B) counter. The total divide ratio, M, is related to values for P, A, and B through the relation M = (P + 1) × A + P × (B – A) = P × B + A, with B ≥ A . The minimum programmable divisor for continuous counting is given by P × ( P – 1 ) = 16 × 15 = 240, and the valid total divide ratio range for the input divider isM = 240 to 65535. Programmable Reference Frequency Divider The crystal oscillator output is divided by the programmable divider and then internally output to the PFD as fR. The programmable reference frequency divider consists of a 13bit reference (R) counter. Because of its design, the valid total divide ratio range for the reference divider is R = 2 to 4095. Page 6 April 2003 FS8160 Phase/Frequency Detector (PFD) The PFD compares an internal input frequency divider output signal, fV, with an internal reference frequency divider output signal, fR, and generates an error signal which is proportional to the phase error between fV and fR. The polarity of the PFD is user-selectable using serial input data control bits (see Table 5 on page 9). The input/output waveforms for a positive polarity PFD (VCO frequency increases with increasing tuning voltage) are shown in Fig. 1. Fig. 1 – Positive polarity PFD input/output waveforms fR fV high-Z DOM, DOA high-Z high-Z Charge Pump The charge pump output sources/sinks current to/from an external loop filter, which converts the charge into a voltage used to control the external VCO’s frequency. When the PLL is locked, the charge pump output is primarily in a high impedance (high-Z) state. The magnitude of the charge pump output current is user-selectable using serial input data control bits (see Table 5 on page 9). Serial Input Data Format The divide ratios for the input (N) and reference (R) dividers are input using an 18-bit serial interface consisting of separate clock (CLK), data (DATA), and latch enable (LE) lines. The format of the serial data is shown in Fig. 2. Fig. 2 – Serial input data format MSB LSB DATA[15:0] 17 21 CB[1:0] 0 Page 7 The data on the DATA line is written to the shift register on the rising edge of the CLK signal and is input with MSB first. The data on the DATA line should be changed on the falling edge of CLK, and LE should be held low while data is being written to the shift register. Data is transferred from the shift register to one of the four (4) frequency divider latches when LE is set high depending upon the state of the control bits (CB[1:0]) as indi- April 2003 FS8160 cated below. Table 1: Latch enable control bits CB[1] 0 0 1 1 CB[0] 0 1 0 1 Latch Location Aux. R Aux. N Main R Main N The definition of the contents of the shift register relating to each particular latch location is listed in the table below. Table 2: Serial data input format First bit 17 Aux. R Aux. N Main R Main N CP_CNTRL[3:0] MAINB[11:0] 16 15 14 13 12 11 Shift Register Bit Location 10 9 8 7 6 5 4 3 2 1 0 AUXA[3:0] MAINR[11:0] MAINA[3:0] 0 1 1 Last bit 0 0 1 0 1 FOLD[3:0] AUXB[11:0] AUXR[11:0]) The 12-bit main and auxiliary reference (R) divider ratios are specified by the MAINR[11:0] and AUXR[11:0] bits, respectively, and are defined in the table below. Table 3: Reference divider ratios Divide Ratio 2 3 MAINR[11:0] and AUXR[11:0] 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 1 1 0 0 1 • 4095 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 Page 8 April 2003 FS8160 Similarly, the 16-bit main and auxiliary input (N) divider ratios are specified by the MAINA[3:0] + MAINB[11:0] and AUXA[3:0] + AUXB[11:0] bits, respectively, and are defined in the table below. Table 4: Input divider ratios Divide Ratio 11 3 4 0 0 10 0 0 9