www.DataSheet4U.com Pre-Production
FM25256
256Kb FRAM Serial 5V Memory Features
256K bit Ferroelectric Nonvolatile RAM • Organized as 32,768 x 8 bits • Unlimited Read/Write Cycles • 10 Year Data Retention • NoDelay™ Writes • Advanced High-Reliability Ferroelectric Process Very Fast Serial Peripheral Interface - SPI • Up to 25 MHz Frequency • Direct Hardware Replacement for EEPROM • SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Write Protection Scheme • Hardware Protection • Software Protection Wide Operating Range • Wide Voltage Operation 4.0V – 5.5V Industry Standard Configurations • Industrial Temperature -40°C to +85°C • 8-pin SOIC (-S) • “Green” 8-pin SOIC (-G)
Description
The FM25256 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM25256 performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. The next bus cycle may start immediately. In addition, the product offers virtually unlimited write endurance. Also, FRAM exhibits much lower power consumption than EEPROM. These capabilities make the FM25256 ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25256 provides substantial benefits to users of serial EEPROM as a hardware drop-in replacement. The FM25256 uses the high-speed SPI bus, which enhances the high-speed write capability of FRAM technology. Device specifications are guaranteed over an industrial temperature range of -40°C to +85°C.
Pin Configuration CS SO WP VSS
1 2 3 4 8 7 6 5
VDD HOLD SCK SI
Pin Name /CS /WP /HOLD SCK SI SO VDD VSS
Function Chip Select Write Protect Hold Serial Clock Serial Data Input Serial Data Output Supply Voltage (4.0 to 5.5V) Ground
Ordering Information
FM25256-S FM25256-G 8-pin SOIC “Green” 8-pin SOIC
This is a product in the pre-production phase of development. Device characterization is complete and Ramtron does not expect to change the specifications. Ramtron will issue a Product Change Notice if any specification changes are made.
Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 www.ramtron.com
Rev. 2.0 Apr. 2005
Page 1 of 13
www.DataSheet4U.com
FM25256
WP CS HOLD SCK
Instruction Decode Clock Generator Control Logic Write Protect
8192 x 32 FRAM Array
Instruction Register
Address Register Counter SI
15
8
Data I/O Register 3 Nonvolatile Status Register
SO
Figure 1. Block Diagram
Pin Descriptions Pin Name /CS I/O Input Description Chip Select: This active low input activates the device. When high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. When low, the device internally activates the SCK signal. A falling edge on /CS must occur prior to every op-code. Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Since the device is static, the clock frequency may be any value between 0 and 25 MHz and may be interrupted at any time. Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for another task. When /HOLD is low, the current operation is suspended. The device ignores any transition on SCK or /CS. All transitions on /HOLD must occur while SCK is low. Write Protect: This active low pin prevents write operations to the status register only. A complete explanation of write protection is provided on pages 6 and 7. Serial Input: All data is input to the device on this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications. * SI may be connected to SO for a single pin data interface. Serial Output: This is the data output pin. It is driven during a read and remains tristated at all other times including when /HOLD is low. Data transitions are driven on the falling edge of the serial clock. * SO may be connected to SI for a single pin data interface. Power Supply (4.0V to 5.5V) Ground
SCK
Input
/HOLD
Input
/WP SI
Input Input
SO
Output
VDD VSS
Supply Supply
Rev. 2.0 Apr. 2005
Page 2 of 13
www.DataSheet4U.com
FM25256
Overview
The FM25256 is a serial FRAM memory. The memory array is logically organized as 32,768 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25256 and a serial EEPROM with the same pinout is the FRAM’s superior write performance and power consumption.
microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25256 operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25256 devices with a microcontroller that has a dedicated SPI port, as Figure 2 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25256 device. For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins together and tie off the Hold pin. Figure 3 shows a configuration that uses only three pins. Protocol Overview The SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25256 will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25256 supports only modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked into the FM25256 on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer. Important: The /CS must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select.
Memory Architecture
When accessing the FM25256, the user addresses 32K locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a twobyte address. The upper bit of the address range is a “don’t care” value. The complete address of 15-bits specifies each byte address uniquely. Most functions of the FM25256 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25256 due to its fast write cycle and high endurance as compared to EEPROM. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25256 contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that VDD is within datasheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip enable active.
Serial Peripheral Interface – SPI Bus
The FM25256 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 25 MHz. This high-speed serial bus provides high performance serial communication to a host
Rev. 2.0 Apr. 2005
Page 3 of 13
www.DataSheet4U.com
FM25256
SCK MOSI MISO
SO SPI Microcontroller
SI
SCK
SO
SI
SCK
FM25256 CS SS1 SS2 HOLD1 HOLD2 HOLD
FM25256 CS HOLD
MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select
Figure 2. System Configuration with SPI port
P1.0 P1.1
Microcontroller
SO
SI
SCK
FM25256 CS P1.2 HOLD
Figure 3. System Configuration without SPI port
SPI Mode 0: CPOL=0, CPHA=0
7
6
5
4
3
2
1
0
SPI Mode 3: CPOL=1, CPHA=1
7
6
5
4
3
2
1
0
Figure 4
