Floppy Disk Controller

FDC37C78 Floppy Disk Controller FEATURES • • • 3.3/5 Volt Operation Intelligent Auto Power Management 2.88MB FDC37C78 Floppy Disk Controller Licensed CMOS 765B Floppy Disk Controller Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core Supports Two Floppy Drives Directly Supports Vertical Recording Format 16 Byte Data FIFO 100% IBM Compatibility DMA Enable Logic Data Rate and Drive Control Registers Swap Drives A and B Non-Burst Mode DMA Option Detects All Overrun and Underrun Conditions Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption Enhanced Digital Data Separator - 2 Mbps (Only Available When VCC = 5V), 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes 48 pin TQFP Package - • • TABLE OF CONTENTS FEATURES...............................................................................................................................................1 GENERAL DESCRIPTION .......................................................................................................................3 PIN CONFIGURATION.............................................................................................................................4 DESCRIPTION OF PIN FUNCTIONS ......................................................................................................6 FUNCTIONAL DESCRIPTION ...............................................................................................................10 FDC37C78 REGISTERS ..................................................................................................................10 HOST PROCESSOR INTERFACE ..................................................................................................10 FLOPPY DISK CONTROLLER .........................................................................................................11 FLOPPY DISK CONTROLLER INTERNAL REGISTERS.................................................................11 COMMAND SET/DESCRIPTIONS .........................................................................................................29 INSTRUCTION SET ...............................................................................................................................32 AUTO POWER MANAGEMENT.............................................................................................................58 CONFIGURATION..................................................................................................................................62 OPERATIONAL DESCRIPTION.............................................................................................................71 MAXIMUM GUARANTEED RATINGS ..............................................................................................71 DC ELECTRICAL CHARACTERISTICS ...........................................................................................71 TIMING DIAGRAMS ...............................................................................................................................75 2 GENERAL DESCRIPTION The SMSC FDC37C78 Floppy Disk Controller utilizes SMSC's proven SuperCell technology for increased product reliability and functionality. The FDC37C78 optimized for motherboard applications. The FDC37C78 supports both 1 Mbps and 2 Mbps data rates and vertical vertical recording operation at 1 Mbps Data Rate. The FDC37C78 incorporates SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, 16 byte data FIFO, on-chip 12 mA bus drivers and two floppy direct drive support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. The FDC37C78 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. The FDC37C78 Floppy Disk Controller incorporates Software Configurable Logic (SCL) for ease of use. Use of the SCL feature allows programmable system configuration of key functions of FDC The FDC37C78 does not require any external filter components, and is, therefore easy to use and offers lower system cost and reduced board area. The FDC37C78 is software and register compatible with SMSC's proprietary 82077AA core. 3 PIN CONFIGURATION RESET 38 nIOW nIOR DRQ nCS 48 nDACK D0 D1 D2 D3 VSS VCC D4 D5 D6 D7 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 47 46 45 44 43 42 41 40 39 37 36 35 34 33 32 31 nMTR0 nDS1/PD nMTR1/IDLE nDIR VCC nSTEP VSS nHDSEL nWGATE nWDATA MEDIA_ID1 MEDIA_ID0 FDC37C78 nDS0 30 29 28 27 26 25 24 DENSEL VSS A0 A1 A2 X1 21 14 15 16 17 18 19 20 22 X2 DRVDEN0 23 nDSKCHG nWRTPRT 4 DRVDEN1 nINDEX VCC VSS nRDATA nTRK0 IRQ TC FDC37C78 PIN OUT FDC37C78 48 Pin FDC PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Note: “n” denotes active low signal. NAME nDACK D0 D1 D2 D3 VSS VCC D4 D5 D6 D7 VCC IRQ TC nTRK0 nINDEX nWRTPRT VSS VCC nDSKCHG nRDATA DRVDEN0 DRVDEN1 DENSEL PIN # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME MEDIA_ID0 MEDIA_ID1 nWDATA nWGATE nHDSEL VSS nSTEP VCC nDIR nMTR1/IDLE nDS1/PD nMTR0 nDS0 RESET X2 X1 VSS A2 A1 A0 nCS nIOR nIOW DRQ 5 DESCRIPTION OF PIN FUNCTIONS DESCRIPTION OF PIN FUNCTIONS PIN NO. 2-5, 8-11 NAME Data Bus 0-7 SYMBOL D0-D7 BUFFER TYPE I/O12 DESCRIPTION The data bus connection used by the host microprocessor to transmit data to and from the chip. These pins are in a high-impedance state when not in the output mode. This active low signal is issued by the host microprocessor to indicate a read operation. This active low signal is issued by the host microprocessor to indicate a write operation. These host address bits determine the I/O address to be accessed during nIOR and nIOW cycles. These bits are latched internally by the leading edge of nIOR and nIOW. This active high output is the DMA request for byte transfers of data between the host and the chip. This signal is cleared on the last byte of the data transfer by the nDACK signal going low (or by nIOR going low if nDACK was already low as in demand mode). An active low input acknowledging the request for a DMA transfer of data between the host and the chip. This input enables the DMA read or write internally. This signal indicates to the chip that DMA data transfer is complete. TC is only accepted when nDACK is low. TC is active high. The interrupt request from the logical device is output on the IRQ signal. Refer to the configuration registers for more information. When enabled, this active low pin serves as an input for an external decoder circuit which is used to qualify address lines above A2. HOST PROCESSOR INTERFACE 46 47 44-42 I/O Read I/O Write I/O Address nIOR nIOW A0-A2 I I I 48 DMA Request DRQ O12 1 n DMA Acknowledge nDACK I 14 Terminal Count TC I 13 Interrupt Request IRQ O12 45 Chip Select Input nCS I 6 DESCRIPTION OF PIN FUNCTIONS PIN NO. 38 NAME Reset SYMBOL RESET BUFFER TYPE IS DESCRIPTION This active high signal resets the chip and must be valid for 500 ns minimum. The effect on the internal registers is described in the appropriate section. The configuration registers are not affected by this reset. Raw serial bit stream from the disk drive, low active. Each falling edge represents a flux transition of the encoded data. This active low high current driver provides the encoded data to the disk drive. Each falling edge causes a flux transition on the media. This high current output selects the floppy disk side for reading or writing. A logic "1" on this pin means side 0 will be accessed, while a logic "0" means side 1 will be accessed. This high current low active output determines the direction of the head movement. A logic "1" on this pin means outward motion, while a logic "0" means inward motion. This active low high current driver issues a low pulse for each track-to-track movement of the head. This input senses that the drive door is open or that the diskette has possibly been changed since the last drive selection. This input is inverted and read via bit 7 of I/O address 3F7H. Indicates the drive and media selected. Refer to configuration registers CR03, CR0B, CR1F. Indicates whether a low (250/300 Kb/s) or high (500 Kb/s) data rate has been selected. This is determined by the IDENT bit in Configuration Register 3. FLOPPY DISK INTERFACE 21 Read Disk Data nRDATA IS 27 Write Data nWDATA OD20 29 Head Select nHDSEL OD20 33 Direction Control nDIR OD20 31 Step Pulse nSTEP OD20 20 Disk Change nDSKCHG IS 22, 23 24 DRVDEN 0, DRVDEN 1 Density Select DRVDEN0, DRVDEN1 DENSEL OD20 OD20 7 DESCRIPTION OF PIN FUNCTIONS PIN NO. 25, 26 NAME Media ID0, Media ID1 SYMBOL MEDIA_ID0, MEDIA_ID1 BUFFER TYPE I DESCRIPTION In Floppy Enhanced Mode 2 - These bits are the Media ID 0,1 inputs. The value of these bits can be read as bits 6 and 7 of the Floppy Tape Register. This active low high current driver allows current to flow through the write head. It becomes active just prior to writing to the diskette. This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the outermost track. This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole. This active low Schmitt Trigger input senses from the disk drive that a disk is write protected. Any write command is ignored. This active low open drain output selects motor drive 0. This active low open drain output selects drive 0. This active low open drain output select motor drive 0. This pin indicates that the part is in the IDLE state and can be powered down. Whenever the part is in this state, IDLE pin is acti