Stereo Audio Power Amplifier

www.DataSheet4U.com EUA5212 2-W Stereo Audio Power Amplifier with Four Selectable Gain Settings DESCRIPTOIN The EUA5212 is a stereo audio power amplifier. When driving 1 W into 8-Ω speakers, the EUA5212 has less than 0.8% THD+N across its specified frequency range. Included within this device is integrated depop circuitry that virtually eliminates transients that cause noise in the speakers. Amplifier gain is internally configured and controlled by way of two terminals (GAIN0 and GAIN1). BTL gain settings of 6dB, 15.5dB, 21.5dB and 27.6dB are provided, while SE gain is always configured as 0dB for headphone drive. An internal input MUX allows two sets of stereo inputs to the amplifier .The HP/LINE terminal allows the user to select which MUX input is active, regardless of whether the amplifier is in SE or BTL mode. In notebook applications, where internal speakers are driven as BTL and the line outputs (often headphone drive) are required to be SE, the EUA5212 automatically switches into SE mode when the SE/ BTL input is activated, and this reduces the gain to 0dB. The EUA5212 consumes only 6 mA of supply current during normal operation. FEATURES 2W per Channel Output Power Into 3-Ω Load Internal Gain Control, Which Eliminates External Gain-Setting Components Input MUX Select Terminal PC-Beep Input Depop Circuitry Integrated Two Input Modes Allowable with Single-Ended or Fully Differential Input Low Supply Current and Shutdown Current Thermal Shutdown Protection TSSOP-24 with Thermal Pad APPLICATIONS Notebook Computers Multimedia Monitors Digital Radios and Portable TVs Block Diagram DS5212 Ver 1.5 Nov. 2004 1 www.DataSheet4U.com EUA5212 Typical Application Circuit Figure 1. Application circuit using single-ended inputs and input MUX Figure 2. Application circuit using differential input DS5212 Ver 1.5 Nov. 2004 2 www.DataSheet4U.com EUA5212 Pin Configurations Package Pin Configurations (Top View) TSSOP-24 with a Thermal Pad exposure on the bottom of the package Pin Description PIN PIN I/O DESCRIPTION BYPASS GAIN0 GAIN1 GND LHPIN LIN LLINEIN LOUT+ LOUTPC-BEEP 11 2 3 1,12 13,24 6 10 5 4 9 14 I I Tap to voltage divider for internal mid-supply bias generator Bit 0 of gain control Bit 1 of gain control Ground connection for circuitry. Connected to thermal pad. I I I O O I HP/ LINE PVDD RHPIN RIN RLINEIN ROUT+ ROUT- 17 7,18 20 8 23 21 16 I I I I I O O SHUTDOWN SE/ BTL VDD 22 15 19 I I I Left channel headphone input, selected when SE/ BTL is held high. Common left input for fully differential input. AC ground for single-ended inputs. Left channel line input, selected when SE/ BTL is held low. Left channel positive output in BTL mode and positive output in SE mode. Left channel negative output in BTL mode and high-impedance in SE mode. The input for PC Beep mode. PC-BEEP is enabled when a > 1-V (peak-to-peak) square wave is input to PC-BEEP or PCB ENABLE is high. HP/LINE is the input MUX control input. When the HP/LINE terminal is held high, the headphone inputs (LHPIN or RHPIN [6, 20]) are active. When the HP/LINE terminal is held low, the line BTL inputs (LLINEIN or RLINEIN [5, 23]) are active. Power supply for output stage. Right channel headphone input, selected when SE/ BTL is held high Common right input for fully differential input. AC ground for single-ended inputs. Right channel line input, selected when SE/ BTL is held low. Right channel positive output in BTL mode and positive output in SE mode. Right channel negative output in BTL mode and high-impedance in SE mode. When held low, this terminal place the entire device, except PC-BEEP detect circuitry, in shutdown mode. Input and output MUX control. When this terminal is held high, the LHPIN or RHPIN and SE output is selected. When this terminal is held low, the LLINEIN or RLINEIN and BTL output are selected. Analog VDD input supply. This terminal needs to be isolated from PVDD to achieve highest performance. DS5212 Ver 1.5 Nov. 2004 3 www.DataSheet4U.com EUA5212 Ordering Information Order Number EUA5212QIR Package Type TSSOP 24 Marking xxxx EUA5212 xxxx EUA5212 Operating Temperature range -40 °C to 85°C EUA5212QIT TSSOP 24 -40 °C to 85°C EUA5212 ¡¼ ¡¼ ¡¼ Packing R: Tape& Reel T: Tube Operating temperature range I: Industry Standard Package Type Q: TSSOP DS5212 Ver 1.5 Nov. 2004 4 www.DataSheet4U.com EUA5212 Absolute Maximum Ratings Supply voltage, VDD------------------------------------------------------------------------------------------------ 6V Input voltage, VI------------------------------------------------------------------------------ –0.3 V to VDD +0.3 V Continuous total power dissipation---------------------------- internally limited (see Dissipation Rating Table) Operating free-air temperature range, TA--------------------------------------------------------- –40¢X to 85¢XC C Operating junction temperature range, TJ ------------------------------------------------------ - –40¢X to 150¢X C C Storage temperature range, Tstg------------------------------------------------------------------ -- –65¢X to 150¢X C C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds----------------------------------------- 260¢X C Dissipation Rating Table TA¡Ø 25°C DERATING FACTOR 3.76 W 33.2 mW/°C PACKAGE PWP TA = 70°C 2.4096 W TA = 85°C 2.1 W Recommended Operating Conditions Min Supply voltage, VDD High-level input voltage, VIH Low-level input voltage, VIL Operating free-air temperature, TA SE/ BTL SHUTDOWN SE/ BTL SHUTDOWN -40 4.5 4 2 3 0.8 85 Max 5.5 Unit V V V °C Electrical Characteristics at Specified Free-air Temperature, VDD = 5V, TA = 25°C Symbol VOO PSRR Parameter Output offset voltage (measured differentially) Power supply rejection ratio High-level input current Low-level input current Supply current Supply current, shutdown mode Conditions VI =0V, AV =2 V/V VDD= 4 V to 5 V VDD=5.5 V, VI = VDD VDD=5.5 V, VI = 0V BTL mode SE mode EUA5212 Min. Typ. Max. 30 68 900 900 6 3 120 8 4 300 Unit mV dB µ µ mA µA IIH IIL IDD IDD(SD) DS5212 Ver 1.5 Nov. 2004 5 www.DataSheet4U.com EUA5212 Operating Characteristics, VDD = 5V, TA = 25°C, RL = 8Ω, Gain =-2V/V, BTL mode Symbol PO THD+N BOM Parameter Output power Total harmonic distortion plus noise Maximum output power bandwidth Supply ripple rejection ratio Conditions THD=1%, RL=4Ω, f=1kHz PO=1W, f=20 Hz to 15 kHz THD=5% f =1kHz, C(BYP)=0.47µF BTL mode EUA5212 Min. Typ. 1.9 0.75% ¡Ö Max. Unit W 15 68 70 43 kHz dB µVRMS Vn Noise output voltage BTL mode C(BYP)=0.47µF, f= 20 kHz to 20 kHz SE mode DS5212 Ver 1.5 Nov. 2004 6 www.DataSheet4U.com EUA5212 Typical Operating Characteristics Figure3 Figure4 Figure 5 Figure 6 Figure 7 DS5212 Ver 1.5 Nov. 2004 Figure 8 7 www.DataSheet4U.com EUA5212 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 DS5212 Ver 1.5 Nov. 2004 Figure 14 8 www.DataSheet4U.com EUA5212 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 DS5212 Ver 1.5 Nov. 2004 Figure 20 9 www.DataSheet4U.com EUA5212 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 DS5212 Ver 1.5 Nov. 2004 Figure 26 10 www.DataSheet4U.com EUA5212 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 DS5212 Ver 1.5 Nov. 2004 Figure 32 11 www.DataSheet4U.com EUA5212 Figure33 Figure 34 Figure 35 Figure 36 Figure 37 DS5212 Ver 1.5 Nov. 2004 12 www.DataSheet4U.com EUA5212 Application Information Gain Setting The gain of the EUA5212 is set by two input terminals, Gain0 and Gain1.The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. Table 1.Gain Setting GAIN0 GAIN1 Input Capacitor, Ci In the typical application an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier, Zi, from a high-pass filter with the corner frequency determined in equation 2. SE/ BTL AV(inv) ZI fc(highpass)= 1 -----------------(2) 2π Z C i i 0 0 1 1 X 0 1 0 1 X 0 0 0 0 1 2v/v 6v/v 12v/v 24v/v 1v/v 91kΩ 45.5kΩ 26kΩ 14kΩ Input Resistance Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest value to over 6 times that value. As a results, if a single capacitor is used in the input high pass filter, the –3 dB or cut off frequency will also change by over 6 times. If an additional resistor is connected from the input pin of the amplifier to ground, as shown in the figure below, the variation of the cut-off frequency will be much reduced. The value of Ci is important to consider as it directly affects the bass (low frequency) performance of the circuit. Consider the example where Zi is 710kΩ and the specification calls for a flat bass response down to 40Hz. Equation 2 is reconfigured as equation 3. 1 Ci = ----------------------------- (3 ) 2 π Z fC i In this example, Ci is 5.6nF so one would likely choose a value in the range of 5.6nF to 1µF. A further consideration for this capacitor is the leakage path from the input source through the input network (Ci) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low- leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at VDD/2, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. The -3dB frequency can be calculated using equation 1: f-3dB = 1 2 π C (R || R ) i ---------------------- (1) If the filter must be more accurate, the value of the capacitor should be increased while the value of the resistor to ground sh