8-BIT MICRO-CONTROLLER

www.DataSheet4U.com EM78P153S OTP ROM EM78P153S 8-BIT MICRO-CONTROLLER Version 1.4 www.DataSheet4U.com EM78P153S OTP ROM Specification Revision History Version 1.1 1.2 1.3 1.4 Initial version Change Initialized Register Values, Internal RC Drift Rate, DC and AC Electrical Characteristic Change Power on reset content Add the Device Characteristic at section 6.3 05/02/2003 06/25/2003 12/31/2003 Content Application Note AN-001 Q & A on ICE153S AN-002 The Set-up Timing and Pin Change Wake-up Function Application AN-003 Internal RC Oscillator Mode This specification is subject to change without prior notice. 2 4. 1.2004 (V1.4) www.DataSheet4U.com EM78P153S OTP ROM 1. GENERAL DESCRIPTION EM78P153S is an 8-bit microprocessor with low-power and high-speed CMOS technology. It is equipped with a 1024*13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. It provides a PROTECTION bit to prevent intrusion of user’s code in the OTP memory as well as 15 OPTION bits to match user’s requirements. With its OTP-ROM feature, the EM78P153S offers users a convenient way of developing and verifying their programs. Moreover, user developed code can be easily programmed with the ELAN writer. This specification is subject to change without prior notice. 3 4. 1.2004 (V1.4) www.DataSheet4U.com EM78P153S OTP ROM 2. FEATURES • 14-lead packages : EM78P153S • Operating voltage range : 2.3V~5.5V • Available in temperature range: 0°C~70°C • Operating frequency range (base on 2 clocks): * Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V. * ERC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V. • Low power consumption: * less then 1.5 mA at 5V/4MHz * typical of 15 µA, at 3V/32KHz * typical of 1µA, during the sleep mode • 1024 × 13 bits on chip ROM • Built-in calibrated IRC oscillators (8MHz, 4MHz, 1MHz, 455KHz ) • Programmable prescaler of oscillator set-up time • One security register to prevent the code in the OTP memory from intruding • One configuration register to match the user’s requirements • 32× 8 bits on chip registers (SRAM, general purpose register) • 2 bi-directional I/O ports • 5 level stacks for subroutine nesting • 8-bit real time clock/counter (TCC) with selective signal sources and trigger edges, and with overflow interrupt • Power down mode (SLEEP mode) • Three available interruptions * TCC overflow interrupt * Input-port status changed interrupt (wake up from the sleep mode) * External interrupt • Programmable free running watchdog timer • 7 programmable pull-high I/O pins • 7 programmable open-drain I/O pins • 6 programmable pull-down I/O pins • Two clocks per instruction cycle • Package type: 14 pins SOP, DIP * 14 pin DIP 300mil: EM78P153SP This specification is subject to change without prior notice. 4 4. 1.2004 (V1.4) www.DataSheet4U.com EM78P153S OTP ROM * 14 pin SOP 150mil: EM78P153SN • The transient point of system frequency between HXT and LXT is around 400KHz. This specification is subject to change without prior notice. 5 4. 1.2004 (V1.4) www.DataSheet4U.com EM78P153S OTP ROM 3. PIN ASSIGNMENTS P50 P67 P66 Vdd P65/OSCI P64/OSCO P63//RST 1 2 3 4 5 6 7 EM78P153S 14 13 12 11 10 9 8 P51 P52 P53 Vss P60//INT P61 P62/TCC Fig. 1 Pin assignment Table 1 Pin description Symbol Vdd Pin No. Type Function 4 - Power supply. * General purpose I/O pin. * External clock signal input. P65/OSCI 5 I/O * Input pin of XT oscillator. * Pull-high/open-drain * Wake up from sleep mode when the status of the pin changes. * General purpose I/O pin. * External clock signal input. P64/OSCO 6 I/O * Input pin of XT oscillator. * Pull-high/open-drain * Wake up from sleep mode when the status of the pin changes. * If set as /RESET and remain at logic low, the device will be under reset. * Wake up from sleep mode when the status of the pin changes. P63//RESET 7 I * Voltage on /RESET must not exceed Vdd during the normal mode. * Internal Pull-high is on if defined as /RESET. * P63 is input pin only * General purpose I/O pin. * Pull-high/open-drain/pull-down. P62/TCC 8 I/O * Wake up from sleep mode when the status of the pin changes. * External Timer/Counter input. * General purpose I/O pin. * Pull-high/open-drain/pull-down. P61 9 I/O * Wake up from sleep mode when the status of the pin changes. * Schmitt Trigger input during the programming mode * General purpose I/O pin. * Pull-high/open-drain/pull-down. P60//INT 10 I/O * Wake up from sleep mode when the status of the pin changes. * Schmitt Trigger input during the programming mode. This specification is subject to change without prior notice. 6 4. 1.2004 (V1.4) www.DataSheet4U.com EM78P153S OTP ROM * External interrupt pin triggered by falling edge. * General purpose I/O pin. 2, 3 I/O * Pull-high/open-drain. * Wake up from sleep mode when the status of the pin changes. * General purpose I/O pin. 1,14~13 I/O * Pull-down 12 I/O * General purpose I/O pin. 11 - *Ground. P66, P67 P50~P53 P53 VSS This specification is subject to change without prior notice. 7 4. 1.2004 (V1.4) www.DataSheet4U.com EM78P153S OTP ROM 4. FUNCTION DESCRIPTION OSCO OSCI Oscillator/Timing Control /RESET WDT timer Prescaler TCC /INT ROM R2 Stack Built-in OSC RAM Interrupt Controller R1(TCC) Instruction Register R3 ALU R4 Instruction Decoder ACC DATA & CONTROL BUS P60 P61 P62/TCC P63//REST P64/OSCO P65/OSCI P66 P67 IOC6 R6 I/O PORT 6 IOC5 R6 I/O PORT 5 P50 P51 P52 P53 Fig. 2 Functional block diagram 4.1 Operational Registers 1. R0 (Indirect Addressing Register) R0 is not a physically implemented register. Its major function is to be an indirect addressing pointer. Any instruction using R0 as a pointer, actually accesses data pointed by the RAM Select Register (R4). 2. R1 (Time Clock /Counter) • Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. • Writable and readable as any other registers. • Defined by resetting PAB (CONT-3). • The prescaler is assigned to TCC if the PAB bit (CONT-3) is reset. • The contents of the prescaler counter is cleared only when a value is written to TCC register. This specification is subject to change without prior notice. 8 4. 1.2004 (V1.4) www.DataSheet4U.com EM78P153S OTP ROM 3. R2 (Program Counter) & Stack • Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in Fig.3. •1024×13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program page is 1024 words long. • R2 is set as all "0"s when at RESET condition. • "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any location within a page. • "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. • "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level stack. • "ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth and tenth bits of the PC are cleared. • "MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC are cleared. • Any instruction that is written to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",⋅⋅⋅⋅⋅) will cause the ninth and tenth bits (A8,A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of a page. • All instructions are single instruction cycle (fclk/2 or fclk/4), except for the instruction that would change the contents of R2. This instruction will need one more instruction cycle. PC (A9 ~ A0) Reset Vector Interrupt Vector 000H 008H User Memory Space Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5 On-chip Program Memory 3FFH Fig. 3 Program counter organization This specification is subject to change without prior notice. 9 4. 1.2004 (V1.4) www.DataSheet4U.com EM78P153S OTP ROM Address R PAGE registers IOC PAGE registers 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 ︰ 2F R0 R1 R2 R3 R4 R5 R6 (TCC) (PC) (Status) (RSR) (Port5) (Port6) Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve RF (Interrupt Status) IOC5 IOC6 Reserve CONT (Control Register) Reserve Reserve Reserve (I/O Port Control Register) (I/O Port Control Register) Reserve Reserve Reserve Reserve IOCB (Pull-down Register) IOCC (Open-drain Control) IOCD (Pull-high Control Register) IOCE (WDT Control Register) IOCF (Interrupt Mask Register) General Registers Fig. 4 Data memory configuration This specification is subject to change without prior notice. 10 4. 1.2004 (V1.4) www.DataSheet4U.com EM78P153S OTP ROM 4. R3 (Status Register) 7 RST 6 GP1 5 GP0 4 T 3 P 2 Z 1 DC 0 C • Bit 7 (RST) Bit for reset type. Set to 1 if wake-up from sleep mode on pin change Set to 0 if wake up from other reset types • Bit6 ~ 5 (GP1 ~ 0) General purpose read/write bits. • Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT time-out. • Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. • Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. • Bit 1 (DC) Auxiliary carry flag • Bit 0 (C) Carry flag 5. R4 (RAM Select Register) • Bits 7 ~ 6 are general-purpose read/write bits. See the configuration of the data memory in Fig. 4. • Bits 5 ~ 0 are used to select registers (address: 00~06, 0F~2F) in the indirect addressing mode. 6. R5 ~ R6 (Port 5 ~ Port 6) • R5 and R6 are I/O registers. • Only the lower 4 bits of R5 are available. • The upper 4 bits of R5 are fixed to 0. • P63 is input only. 7. RF (Interrupt Status Register) 7 6 5 4 3 2 EXIF 1 ICIF 0 TCIF “1” mea