8M x 32 DDR SDRAM

EtronTech Revision History Revision 0.6(May, 2006) Preliminary Spec Delete confidential wording. EM6AA320 Revision 0.5(May, 2003) Preliminary Spec Revised the AC Timing of tCLK at CL=4 for pure VDD/VDDQ=2.8V spec. Revision 0.4(May, 2003) Preliminary Spec Revised the AC Timing of tCLK at CL=4 for pure VDD/VDDQ=2.5V spec. Revision 0.3(March, 2003) Preliminary Spec Separated pure VDD/VDDQ=2.8V spec for graphics application. Revision 0.2(March, 2003) Preliminary Spec Separated pure VDD/VDDQ=2.5V spec for mobile PC graphics application. Initially defined VDD=VDDQ=2.5V 275MHz(-3.6ns) preliminary specification. Combined VDD=VDDQ=2.5V 200MHz(-5ns) and 250MHz(-4ns) specification from rev. 0.1 for both 2.8V and 2.5V. Revision 0.1(February, 2003) Preliminary Spec Defined EM6AA320BI-3.6(275MHz). Added special code “M” in EM6AA320BI-4M for indicating 2.5V power supply. Added special code “M” in EM6AA320BI-5M for indicating 2.5V power supply. Removed EM6AA320BI-3.5(285MHz). Revised the DC current of IDD2P, IDD2N, IDD3P, IDD3N, IDD4R and IDD4W for all speed grade. Revision 0.0(July, 2002) Preliminary Spec Initially defined target specification. EtronTech Features • Fast clock rate: 300/275/250/200 MHz • Differential Clock CK & CK# input • 4 Bi-directional DQS. Data transactions on both edges of DQS (1DQS / Byte) • DLL aligns DQ and DQS transitions • Edge aligned data & DQS output • Center aligned data & DQS input • 4 banks operation • Programmable mode and extended mode registers - CAS# Latency: 3, 4, 5 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleave • Full page burst length for sequential type only • Start address of full page burst should be even • All inputs except DQ’s & DM are at the positive edge of the system clock • No Write-Interrupted by Read function • 4 individual DM control for write masking only • Auto Refresh and Self Refresh • 4096 refresh cycles / 32ms • Power supplies : VDD = 2.8V ± 5% VDDQ = 2.8V ± 5% • Interface : SSTL_2 I/O compatible • Standard 144-ball FBGA package EM6AA320 8M x 32 DDR SDRAM Preliminary (Rev 0.6 5/2006) Overview The EM6AA320 DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 256 Mbits. It is internally configured as a quad 2M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK#. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command, which is then followed by a Read or Write command. The EM6AA320 provides programmable Read or Write burst lengths of 2, 4, 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, EM6AA320 features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics applications. Ordering Information Part Number (*) EM6AA320BI-3.3S (*) EM6AA320BI-3.6S (*) EM6AA320BI-4S (*) EM6AA320BI-5S Frequency 300MHz 275MHz 250MHz 200MHz Power Supply VDD 2.8V VDDQ 2.8V Package FBGA * : S indicates stack die package Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech 1 A DQS0 2 DM0 3 VSSQ 4 DQ3 5 DQ2 8Mx32 DDR SDRAM EM6AA320 10 VSSQ 11 DM3 12 DQS3 Pin Assignment (FBGA 144Ball Top View) 6 DQ0 7 DQ31 8 DQ29 9 DQ28 B DQ4 VDDQ NC VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ NC VDDQ DQ27 C DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25 D DQ7 VDDQ VDD VSS VSSQ VSS VSS VSSQ VSS VDD VDDQ DQ24 E DQ17 DQ16 VDDQ VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSSQ VDDQ DQ15 DQ14 F DQ19 DQ18 VDDQ VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSSQ VDDQ DQ13 DQ12 G DQS2 DM2 NC VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSSQ NC DM1 DQS1 H DQ21 DQ20 VDDQ VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSSQ VDDQ DQ11 DQ10 J DQ22 DQ23 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ9 DQ8 K CAS# WE# VDD VSS A10 VDD VDD NC VSS VDD NC NC L RAS# NC NC BA1 A2 A11 A9 A5 NC CK CK# NC M CS# NC BA0 A0 A1 A3 A4 A6 A7 A8/AP CKE VREF Pin Assignment by Name (FBGA 144Ball) Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location A0 M4 DQ6 C1 DQ24 D12 CK L10 VDDQ B6 VSS E5 VSS J7 VSSQ G4 A1 M5 DQ7 D1 DQ25 C12 CK# L11 VDDQ B7 VSS E6 VSS J8 VSSQ G9 A2 L5 DQ8 J12 DQ26 C11 CKE M11 VDDQ B9 VSS E7 VSS K4 VSSQ H4 A3 M6 DQ9 J11 DQ27 B12 CS# M1 VDDQ B11 VSS E8 VSS K9 VSSQ H9 A4 M7 DQ10 H12 DQ28 A9 RAS# L1 VDDQ D2 VSS F5 VSSQ A3 VSSQ J4 A5 L8 DQ11 H11 DQ29 A8 CAS# K1 VDDQ D11 VSS F6 VSSQ A10 VSSQ J9 A6 M8 DQ12 F12 DQ30 B8 WE# K2 VDDQ E3 VSS F7 VSSQ C3 NC B3 A7 M9 DQ13 F11 DQ31 A7 VREF M12 VDDQ E10 VSS F8 VSSQ C4 NC B10 A8/AP M10 DQ14 E12 DQS0 A1 VDD C6 VDDQ F3 VSS G5 VSSQ C5 NC G3 A9 L7 DQ15 E11 DQS1 G12 VDD C7 VDDQ F10 VSS G6 VSSQ C8 NC G10 A10 K5 DQ16 E2 DQS2 G1 VDD D3 VDDQ H3 VSS G7 VSSQ C9 NC K8 A11 L6 DQ17 E1 DQS3 A12 VDD D10 VDDQ H10 VSS G8 VSSQ C10 NC K11 DQ0 A6 DQ18 F2 DM0 A2 VDD K3 VDDQ J3 VSS H5 VSSQ D5 NC K12 DQ1 B5 DQ19 F1 DM1 G11 VDD K6 VDDQ J10 VSS H6 VSSQ D8 NC L2 DQ2 A5 DQ20 H2 DM2 G2 VDD K7 VSS D4 VSS H7 VSSQ E4 NC L3 DQ3 A4 DQ21 H1 DM3 A11 VDD K10 VSS D6 VSS H8 VSSQ E9 NC L9 DQ4 B1 DQ22 J1 BA0 M3 VDDQ B2 VSS D7 VSS J5 VSSQ F4 NC L12 DQ5 C2 DQ23 J2 BA1 L4 VDDQ B4 VSS D9 VSS J6 VSSQ F9 NC M2 3 Rev 0.6 May 2006 EtronTech Block Diagram 8Mx32 DDR SDRAM EM6AA320 Column Decoder De co de r Ro w 4096 X 512 X 32 CELL ARRAY (BANK #0) Sense Amplifier CK CK# CKE CS# RAS# CAS# WE# DLL CLOCK BUFFER CONTROL SIGNAL GENERATOR Sense Amplifier COMMAND DECODER MODE REGISTER De co de r Ro w 4096 X 512 X 32 CELL ARRAY (BANK #1) Column Decoder COLUMN COUNTER A8/A P Column Decoder De co de r Ro w A0 A 10 A 11 B A0 B A1 ADDRESS BUFFER 4096 X 512 X 32 CELL ARRAY (BANK #2) Sense Amplifier REFRESH COUNTER DQS0~3 DATA STR OBE BUFFER DQ0 DQ31 Sense Amplifier DQ BUFFER De co de r Ro w 4096 X 512 X 32 CELL ARRAY (BANK #3) Column Decoder │ DM 0~3 4 Rev 0.6 May 2006 EtronTech Pin Descriptions Symbol CK, CK# Type Input 8Mx32 DDR SDRAM EM6AA320 Table 1. Pin Details of EM6AA320 Description Differential Clock: CK, CK# are driven by the system clock. All SDRAM input commands are sampled on the positive edge of CK. Both CK and CK# increment the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. Bank Select: BA0 and BA1 defines to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. They also define which Mode Register or Extended Mode Register is loaded during a Mode Register Set command. Address Inputs: A0-A11 are sampled during the Bank Activate command (row address A0-A11) and Read/Write command (column address A0-A7, and A9 with A8 defining Auto Precharge) to select one location out of the memory array in the respective bank. During a Precharge command, A8 is sampled to determine if all banks are to be precharged (A8 = HIGH). The address inputs also provide the opcode during a Mode Register Set or Extended Mode Register Set command. Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the positive edges of CK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH" either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. Column Address Strobe: The CAS# signal defines the operation commands in conjunction with the RAS# and WE# signals and is latched at the positive edges of CK. When RAS# is held "HIGH" and CS# is asserted "LOW" the column access is started by asserting CAS# "LOW" Then, the Read or Write command is selected by asserting WE# "HIGH " or “LOW". Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. Bidirectional Data Strobe: The DQSx signals are mapped to the following data bytes: DQS0 to DQ0-DQ7, DQS1 to DQ8-DQ15, DQS2 to DQ16-DQ23, DQS3 to DQ24-DQ31. Data Input Mask: DM0-DM3 are byte specific. Input data is masked when DM is sampled HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2 masks D