8M x 16 DDR Synchronous DRAM

EtronTech Features • • • • • • • • Fast clock rate: 300/275/250/200MHz Differential Clock CK & /CK Bi-directional DQS DLL enable/disable by EMRS Fully synchronous operation Internal pipeline architecture Four internal banks, 1M x 16-bit for each bank Programmable Mode and Extended Mode registers - /CAS Latency: 3, 4 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved Individual byte write mask control DM Write Latency = 0 Auto Refresh and Self Refresh 4096 refresh cycles / 32ms Precharge & active power down Power supplies: VDD & VDDQ = 2.5V ± 5% Interface: SSTL_2 I/O Interface Package: 66 Pin TSOP II, 0.65mm pin pitch Lead-free Package is available. EM6A9160 (Rev. 1.4 May/2006) 8M x 16 DDR Synchronous DRAM (SDRAM) Pin Assignment (Top View) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BS0 BS1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS • • • • • • • • • Ordering Information Part Number EM6A9160TS-3.3/3.3G* EM6A9160TS-3.6/3.6G EM6A9160TS-4/4G EM6A9160TS-5/5G Clock Frequency 300MHz 275MHz 250MHz 200MHz Data Rate 600Mbps/pin 550Mbps/pin 500Mbps/pin 400Mbps/pin Package TSOP II TSOP II TSOP II TSOP II Note : “G” indicates Pb-free package Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech Overview EM6A9160 The EM6A9160 SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128 Mbits. It is internally configured as a quad 2M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and /CK. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM6A9160 provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, EM6A9160 features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics applications. 2 Rev. 1.4 May 2006 EtronTech Block Diagram 8Mx16 DDR SDRAM EM6A9160 Column Decoder Row Decoder Row Decoder Row Decoder Row Decoder CK /CK CK /CS /RA /CA /WE DLL CLOCK BUFFER CONTROL SIGNAL GENERATOR 2Mx16 CELL ARRAY (BANK #0) Sense Amplifier COMMAND DECODER MODE REGISTER Column Decoder 2Mx16 CELL ARRAY (BANK #1) Sense Amplifier A10 or AP COLUMN COUNTER A0 to A11 BS0 BS1 ADDRESS BUFFER Column Decoder 2Mx16 CELL ARRAY (BANK #2) Sense Amplifier REFRESH COUNTER LDQS UDQS DATA STROBE BUFFER DQ BUFFER Column Decoder 2Mx16 CELL ARRAY (BANK #3) Sense Amplifier DQ0 to DQ15 LDM UDM 3 Rev. 1.4 May 2006 EtronTech Pin Descriptions Symbol CK, /CK Type Input 8Mx16 DDR SDRAM EM6A9160 Table 1. Pin Details of EM6A9160 Description Differential Clock: CK, /CK are driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. Both CK and /CK increment the internal burst counter and controls the output registers. Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CK signal. If CKE goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. Bank Select: BS0 and BS1 defines to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge). Chip Select: /CS enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when /CS is sampled HIGH. /CS provides for external bank selection on systems with multiple banks. It is considered part of the command code. Row Address Strobe: The /RAS signal defines the operation commands in conjunction with the /CAS and /WE signals and is latched at the positive edges of CK. When /RAS and /CS are asserted "LOW" and /CAS is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the /WE signal. When the /WE is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the /WE is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. Column Address Strobe: The /CAS signal defines the operation commands in conjunction with the /RAS and /WE signals and is latched at the positive edges of CK. When /RAS is held "HIGH" and /CS is asserted "LOW," the column access is started by asserting /CAS "LOW." Then, the Read or Write command is selected by asserting /WE "HIGH " or LOW"." Write Enable: The /WE signal defines the operation commands in conjunction with the /RAS and /CAS signals and is latched at the positive edges of CK. The /WE input is used to select the BankActivate or Precharge command and Read or Write command. Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15. Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15. Data I/O: The DQ0-DQ15 input and output data are synchronized with the positive edges of CK and /CK. The I/Os are byte-maskable during Writes. CKE Input BS0, BS1 A0-A11 Input Input /CS Input /RAS Input /CAS Input /WE Input LDQS, UDQS LDM, UDM DQ0 - DQ15 Input / Output Input Input / Output 4 Rev. 1.4 May 2006 EtronTech VDD VSS VDDQ VSSQ VREF NC Supply Supply Supply Supply Supply Ground 8Mx16 DDR SDRAM EM6A9160 Power Supply: +2.5V ±5% DQ Power: +2.5V ±5%. Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Reference Voltage for Inputs: +0.5*VDDQ No Connect: These pins should be left unconnected. 5 Rev. 1.4 May 2006 EtronTech Operation Mode 8Mx16 DDR SDRAM EM6A9160 Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode Register Set Extended MRS No-Operation Burst Stop Device Deselect AutoRefresh SelfRefresh Entry SelfRefresh Exit State Idle(3) Any Any Active(3) Active(3) Active(3) Active(3) Idle Idle Any Active(4) Any Idle Idle Idle (SelfRefresh) CKEn-1 CKEn UDM UDM BS0,1 A10 A0-9,11 /CS /RAS /CAS /WE H H H H H H H H H H H H H H L H L H L H X X X X X X X X X X X X H L H L H L H X X X X X X X X X X X X X X X X X X X X L X X X X X X X X X X X X X X X X X X X L X X X X X X X X X X X V V X V V V V Row address L H L H L H X X Column address (A0 ~ A8) Column address (A0 ~ A8) L L L L L L L L L L L L H H H H L L H H X L L X H X H X H X V X H X X H H H L L L L L L H H X L L X H X H X H X V X H X X H L L L L H H L L H L X H H X H X H X H X V X H X X OP code OP code X X X X X X X X X X X X X X X X X X X X X X L L H L L H L H L H L H L H L X Precharge Power Down Mode Entry Precharge Power Down Mode Exit Active Power Down Mode Entry Active Power Down Mode Exit Idle Any (PowerDown) Active Any (PowerDown) Data Input Mask Disable Data Input Mask Enable(5) Active Active H X H H X X X X Note: 1. V=Valid data, X=Don't Care, L=Low level, H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. LDM and UDM can be enable respectively. 6 Rev. 1.4 May 2006 EtronTech Mode Register Set (MRS) 8Mx16 DDR SDRAM EM6A9160 The mode register is divided into various fields depending on functionality. Burst Length Field (A2~A0) • This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8. A2 0 0 0 0 1 1 1 1 • A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length Reserved 2 4 8 Reserved Reserved Reserved Reserved Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, both Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode support burst length of 2,4 and 8. A3 0 1 Addressing Mode Sequential Interleave --- Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device. The internal column address is varied by the Burst Length as shown in the following table. Data n Column Addres