4M x 32 Hand-Held Low Power SDRAM

EtronTech Features Clock rate: 133/125/100 MHz Fully synchronous operation Internal pipelined architecture Four internal banks (1M x 32bit x 4bank) Programmable Mode - CAS# Latency: 1, 2 & 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential & Interleave - Burst-Read-Single-Write - Driving Strenght : Full & Half - PASR (Partial Array Self Refresh) - TCSR (Temperature Compensated Self Refresh) • Burst stop function • Individual byte controlled by DQM0-3 • Auto Refresh and Self Refresh • • • • • EM66932A Preliminary (Rev 0.1 June/2003) • 4096 refresh cycles/64ms • Single 3.0V, or 3.3V power supply • Interface: LVTTL •Package : 90 ball-FBGA, 11x13mm, Lead Free 4M x 32 Hand-Held Low Power SDRAM (LPSDRAM) Ordering Information Part Number EM66932ABG-7.5G EM66932ABG-8G EM66932ABG-1H/LG Frequency 133MHz 125MHz 100MHz Package 11x13 BGA 11x13 BGA 11x13 BGA Pin Assignment : Top View 1 A B C D E F G H J K L M 2 3 4 5 6 7 8 9 DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS VDD VDDQ DQ22 DQ17 NC A2 A10 NC BA0 CAS# VDD DQ6 DQ1 VDDQ VDD DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 CS# WE# DQ7 DQ5 DQ3 VSSQ DQ0 DQ21 DQ19 VDDQ VDD1Q VSSQ VDD A1 A11 RAS# DQM0 VSSQ VDDQ VDDQ DQ4 DQ2 N P R Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech Overview 4M x 32 HH LPSDRAM EM66932A The EM66932A Hand-held LPSDRAM is a 128M bits high-speed CMOS synchronous DRAM with low power consumption organized as 1,048,576 words by 32 bits by 4 banks. The Hand-held functions are new features of the size of the memory array and the refresh period during Self-Refresh to be programmable by which the self refresh current is drastically reduced. High data transfer rate is achieved by the pipeline architecture with a synchronous interface, burst oriented Read and write accesse, muti banks operation and programmable burst lengths. The EM66932A provides Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. Through the programming burst type, burst length, CAS latency, and driving strength in mode register and extended mode register, a variety with high performance is fulfilled and useful in a variety of wide bandwidth, high performance and low power application. Block Diagram Column Row Decoder Decoder 4096 X 256 X 32 CELL ARRAY (BANK #0) Sense Amplifier CL K CLO CK BUFFER CO N T R OL S IG N A L GE N ER A T OR Sense Row Decoder CKE CS # RA S# CA S# WE# Amplifier CO M M A ND DECODER MODE R E G IS T E R 4096X 256 X 32 CELL ARRAY (BANK #1) Column Decoder CO LU MN COUN TER A 1 0 /A P Column Row Decoder Decoder A0 A9 A10 A11 BA0 BA1 ADDRESS BUFFER 4096 X 256 X 32 CELL ARRAY (BANK #2) Sense Amplifier REFRESH COUN TER Sense DQ BUFFER DQ 0 D Q31 Row Decoder Amplifier 4096 X 256 X 32 CELL ARRAY (BANK #3) Column Decoder Preliminary │ D Q M 0 ~3 2 Rev 0.1 June 2003 EtronTech Pin Descriptions Symbol Type Description CLK 4M x 32 HH LPSDRAM EM66932A Table 1. Pin Details of 4Mx32 HH LPSDRAM Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low standby power. Input Bank Select: BA0 and BA1 defines to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. The bank address BA0 and BA1 is used latched in mode register set. CKE BA0, BA1 A0-A11 Input Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0A11) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one location out of the 1M available in the respective bank. During a Precharge command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH). The address inputs also provide the op-code during a Mode Register Set or Special Mode Register Set command. CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. Input Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. Input Column Address Strobe: The CAS# signal conjunction with the RAS# and WE# signals and When RAS# is held "HIGH" and CS# is asserted asserting CAS# "LOW." Then, the Read or Write "LOW" or "HIGH." defines the operation commands in is latched at the positive edges of CLK. "LOW," the column access is started by command is selected by asserting WE# RAS# CAS# WE# Input Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. DQM0 - Input Data Input/Output Mask: Data Input Mask: DM0-DM3 are byte specific. Input data is DQM3 masked when DM is sampled HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2 masks DQ23-DQ16, DM1 masks DQ15-DQ8, and DM0 masks DQ7-DQ0. DQ0- Input/ Data I/O: The DQ0-31 input and output data are synchronized with the positive edges of DQ31 Output CLK. The I/Os are byte-maskable during Reads and Writes. NC VDDQ No Connect: These pins should be left unconnected. Supply DQ Power: Provide isolated power to DQs for improved noise immunity. Preliminary 3 Rev 0.1 June 2003 EtronTech VSSQ VDD VSS Supply Ground 4M x 32 HH LPSDRAM EM66932A Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. Supply Power Supply: +3.0V±0.3V, or +3.3V±0.3V Preliminary 4 Rev 0.1 June 2003 EtronTech Operation Mode 4M x 32 HH LPSDRAM EM66932A Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode Register Set No-Operation Burst Stop Device Deselect AutoRefresh SelfRefresh Entry SelfRefresh Exit State Idle(3) Any Any Active(3) Active(3) Active(3) Active(3) Idle Any Active(4) Any Idle Idle Idle (SelfRefresh) CKEn-1 CKEn DQM(6) BS0,1 A10 A11, A9-0 CS# RAS# CAS# WE# H H H H H H H H H H H H H L H H L L H X X X X X X X X X X X H L H L L H H X X X X X X X X X X X X X X X X X X X L X X X X X X X X X X X V V X V V V V Row address L H L H L H X X Column address (A0 ~ A7) Column address (A0 ~ A7) L L L L L L L L L L L H H H H L H H X L L X H X H X H X X H X H H H L L L L L H H X L L X H X H X H X X H X H L L L L H H L H L X H H X H X H X H X X H X X OP code X X X X X X X X X X X X X X X X X X X X X X L L H L L H L H L H L X H L X Clock Suspend Mode Entry Active Any(5) Active Any (PowerDown) Power Down Mode Entry Clock Suspend Mode Exit Power Down Mode Exit Data Write/Output Enable Data Mask/Output Disable Active Active H X H X X X X X X Note: 1. V = Valid, X = Don't care, L = Logic low, H = Logic high 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BA signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode. 6. DQM0-3 Preliminary 5 Rev 0.1 June 2003 EtronTech Commands 1 4M x 32 HH LPSDRAM EM66932A BankActivate (RAS# = "L", CAS# = "H", WE# = "H", BA 0,1= Bank, A0-A11 = Row Address) The BankActivate command activates the idle bank designated by the BA0,1 (Bank Select) signal. By latching the row address on A0 to A11 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.) from the time of bank activation. A subsequent BankActivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). The minimum time interval between successive BankActivate commands to the same bank is defined by tRC(min.). The SDRAM has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of the four banks. tRRD(min.) specifies t