Ultra Low Power 8-pin Microcontroller

R EM MICROELECTRONIC - MARIN SA EM6682 Ultra Low Power 8-pin Microcontroller Features True Low Power: 4.0 µA active mode 3.0 µA standby mode 0.35 µA sleep mode @ 1.5V, 32kHz, 25°C Stable RC oscillator 32 - 800kHz Prescaler Figure 1. Architecture ROM 1536 x 16Bit RAM 80 x 4Bit VDD VDD Power Supply Voltage reg. Low Supply Voltage 0.9 V to 5.5 V Medium voltage version: 1.4V to 5.5V Low voltage version: 0.9V to 1.8V No external component needed Available in TSSOP-8/14, SO-8/14 packages and die 4-bit ADC or 12 levels Supply Voltage Level Detector (SVLD) Max 4 (5*) outputs with 2 high drive outputs of 10mA Max. 5 (6*) inputs Sleep Counter Reset (automatic wake-up from sleep mode (EM patent)) Mask ROM 1536 × 16 bits RAM 80 × 4 bits Internal RC oscillator 32 kHz – 800 kHz 2 clocks per instruction cycle 72 basic instructions External CPU clock source possible Watchdog timer (2 sec) Power-On-Reset with Power-Check on Start-Up 3 wire serial port , 8 bit, master and slave mode Universal 10-bit counter, PWM, event counter Prescaler down to 1 Hz (freq. = 32 kHz) Frequency output 1Hz, 2048 Hz, Fosc, PWM 6 internal interrupt sources ( 2×10-bit counter, 2× prescaler, SVLD, Serial Interface) 2 external interrupt sources (port A) Power on Reset Sleep Counter Reset Watchdog 10-Bit Univ Count/Timer Core EM6600 4-bit ADC Interrupt Controller SVLD check Port A Serial Interface Reset PA2 PA3 PA4 *PA5 PA0 PA1 PA1 & PA2: high-drive outputs (10mA) * PA5 available only in 14-pin package and in die Figure 2. Pin Configuration PA0 1 2 3 4 8 V DD V REG PA4 V SS (reset) TSSOP-8, SO-8 PA1 PA2 PA3 EM6682 7 6 5 Description The EM6682 is an ultra-low voltage, low power microcontroller coming in a package as small as 8-pin TSSOP and working up to 0.4 MIPS. It comes with an integrated 4-bit ADC and 2 high drive outputs of 10mA and it requires no external component. It has a sleep counter reset allowing automatic wake-up from sleep mode. It is designed for use in battery-operated and field-powered applications requiring an extended lifetime. A high integration level make it an ideal choice for cost sensitive applications. The EM6682 contains the equivalent of 3kB mask ROM and a RC oscillator with frequencies between 32 and 800kHz selectable by metal option or register. It also has a power-on reset, watchdog timer, 10 bit up/down counter, PWM and several clock functions. Tools include windows-based simulator and emulator. NC PA0 PA1 PA2 PA3 NC NC 1 2 3 4 5 6 7 14 13 12 NC V DD V REG PA5 PA4 V SS NC (reset) TSSOP-14, SO-14 EM6682 11 10 9 8 Typical Applications Household appliances Safety and security devices Automotive controls Sensor interfaces Watchdog Intelligent ADC Driver (LED, triac) The EM6682 simulator is usable for most of the EM6682 functions. Copyright © 2006, EM Microelectronic-Marin SA 1 www.emmicroelectronic.com R EM6682 EM6682 at a glance Power Supply - Low voltage low power architecture including internal voltage regulator - 1.4 V to 5.5 V in medium voltage version - 0.9 V to 1.8 V in low voltage version - 4.0 µA in active mode - 3.5 µA in standby mode - 0.35 µA in sleep mode @ 1.5V, 32kHz, 25°C 4(5)-Bit I/O PA[3:0] & PA[4] / PA[5]* - Direct input read on the port terminals - 2 Debounce function available muxed on 4 inputs - 2 Interrupt request on positive or negative edge - Pull-up or pull-down or none selectable by register, except PA[4] where pullup/down is mask or register selection - 2 Test variables (software) for conditional jumps - PA[1] and PA[3/4] are inputs for the event counter - PA[3/4] Reset input (register selectable) - All outputs can be put tri-state (default) - Selectable pull-downs in input mode - CMOS or Nch. open drain outputs - Weak pull-up selectable in Nch. open drain mode RAM - 80 x 4 bit, directly addressable ROM - 1536 x 16 bit (~3k Byte), metal mask programmable CPU - 4-bit RISC architecture - 2 clock cycles per instruction (CPI=2) - 72 basic instructions 4-bit ADC & Voltage Level Det. (SVLD) - External voltage compare from PA[4] input possible (low resolution 4 bit AD converter) - Levels above Vdd min are available for SVLD - Used for Power Check after POR (level 9 or level 5 selectable by metal option) - Busy flag during measure - Interrupt generated if SVLD measurement low Main Operating Modes and Resets - Active mode (CPU is running) - Standby mode (CPU in halt, peripherals running) - Sleep mode (no clock, reset state, data kept) - Initial Power-On-Reset with Power-Check - power-check after any reset settable by metal option - Watchdog reset (logic) - Reset terminal (software option on PA[3/4]) - Sleep Counter reset from Sleep mode - Wakeup on change from Sleep mode 10-Bit Universal Counter - 10, 8, 6 or 4 bit up/down counting - Parallel load - Event counting (PA[1] or PA[3/4]) - 8 different input clocks - Full 10 bit or limited (8, 6, 4 bit) compare function - 2 interrupt requests (on compare and on 0) - Hi-frequency input on PA[1] and PA[3/4] - Pulse width modulation (PWM) output - Metal option for bit0 don’t care, reduces timer by 1 bit Prescaler - Divider (4 stages) to best fit CPU clock (32kHz – 1MHz to 32kHz system clock to keep peripherals timing close to specification - 15 stage system clock divider from 32kHz down to 1Hz - 2 Interrupt requests (3 different frequencies) - Prescaler reset (4kHz to 1Hz) Interrupt Controller - 2 external and 6 internal interrupt request sources - Each interrupt request can individually be masked - Each interrupt flag can individually be reset - Automatic reset of each interrupt request after read - General interrupt request to CPU can be disabled - Automatic enabling of general interrupt request flag when going into HALT mode 8-Bit Serial Interface - 3 wire (Clock, DataIn , DataOut) master/slave mode - READY output during data transfer - Maximum shift clock is equal to the main system clock - Interrupt request to the CPU after 8 bit data transfer - Supports different serial formats - pins shared with general 4 bit PA[3:0] I/O port Sleep Counter Reset (SCR) - wake up the EM6682 from sleep mode - 4 timings selectable by register - Inhibit SCR by register Oscillator - RC Oscillator range: 32/50kHz to 500/800kHz (metal or register selectable from 32/50, 64/100, 128/200, 256/400 or 500/800 kHz typ. for CPU clock) - No external components are necessary - Temperature compensated - External clock source possible from PA1 Package form available - TSSOP-8/14 - SO-8/14 - Die form (9 pin possible due to additional I/O pin) NB: All frequencies written in this document are related to a typical system clock of 32 kHz ! Copyright © 2005, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com R EM6682 Table of Contents FEATURES______________________________ 1 1H DESCRIPTION ___________________________ 1 2H 8.4.2 8.4.3 PWM Characteristics__________________429 PWM example _______________________529 9H4 0H5 51H 52H EM6682 AT A GLANCE ____________________ 2 3H 1. 2. 2.1 2.2 2.3 3. 4. 4.1 4.2 4.3 4.4 4.5 4.6 5. 5.1 5.2 5.3 6. 6.1 6.2 PIN DESCRIPTION FOR EM6682 _______ 4 4H OPERATING MODES ________________ ACTIVE MODE_______________________ STANDBY (HALT) MODE _______________ SLEEP MODE _______________________ POWER SUPPLY____________________ 5H 6H 7H 8H 9H 10H 5 5 5 5 6 8.5 COUNTER SETUP _____________________ 30 8.6 10-BIT COUNTER REGISTERS ____________ 31 9. SVLD / 4-BIT ADC __________________ 33 9.1 SVLD TRIM: ________________________ 35 FIGURE 25. SVLD TIMING IN “ADC” MODE WHEN SVLDEN SET @ “1” ___________________ 36 10. RAM _____________________________ 37 53H 54H 5H 56H RESET ____________________________ 7 POR WITH POWER-CHECK RESET_________ 8 INPUT PORT A RESET __________________ 9 DIGITAL WATCHDOG TIMER RESET ________ 9 SLEEP COUNTER RESET _______________ 10 WAKE-UP ON CHANGE ________________ 10 THE CPU STATE AFTER RESET __________ 10 OSCILLATOR AND PRESCALER _____ 11 RC OSCILLATOR OR EXTERNAL CLOCK_____ 11 SPECIAL 4 STAGE FREQUENCY DIVIDER ____ 12 PRESCALER ________________________ 13 INPUT AND OUTPUT PORT A ________ 14 INPUT / OUTPUT PORT OVERVIEW ________ 14 PORTA AS INPUT AND ITS MULTIPLEXING ___ 15 1H 12H 13H 14H 15H 16H 17H 18H 19H 20H 21H 2H 23H 11. 11.1 12. 13. 14. 14.1 INTERRUPT CONTROLLER __________ 38 INTERRUPT CONTROL REGISTERS _________ 39 PERIPHERAL MEMORY MAP _________ 40 57H 58H 59H ACTIVE SUPPLY CURRENT TEST _____ 43 60H MASK OPTIONS ____________________ 44 INPUT / OUTPUT PORTS ________________ 44 61H 62H 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.11 Debouncer __________________________215 IRQ on Port A _______________________216 Pull-up/down ________________________216 Software test variables ________________217 Port A for 10-Bit Counter _______________217 Port A Wake-Up on change_____________217 Port A for Serial Interface ______________317 Port A for External Reset_______________317 Port PA[4] as Comparator Input _________317 Reset and Sleep on Port A _____________317 Port A Blocked Inputs _________________317 4H2 5H2 6H2 7H2 8H2 9H2 0H3 1H3 2H3 3H 4H3 35H 14.1.1 14.1.2 14.1.3 14.1.4 14.1.5 14.1.6 14.1.7 14.1.8 14.1.9 14.1.10 14.1.11 Port A Metal Options __________________644 RC oscillator Frequency Option _________646 Debouncer Frequency Option ___________646 Power-Check Level Option _____________646 ADC/SVLD Voltage Level #15___________646 Counter Update option ________________646 No regulator option ___________________647 SVLD level set_______________________747 Bit 0 don’t care ______________________747 Counter clock source _________________748 Power check level init _________________748 3H6 4H6 5H6 6H 7H6 8H6 9H6 0H7 1H7 2H7 3H7 74H 6.3 6.4 7. 7.1 7.2 7.3 8. 8.1 8.2 8.3 8.4 PORTA AS OUTPUT AND ITS MULTIPLEXING _ 18 CMOS / Nch. Open Drain Output ________318 6H3 6.3.1 PORT A REGISTERS___________________ SERIAL PORT _____________________ GENERAL FUNCTIONAL DESCRIPTION______ DETAILED FUNCTIONAL DESCRIPTION______ 37H 38H 39H 40H 42H 19