Ultra Low Power Multi I/O Microcontroller

EM MICROELECTRONIC - MARIN SA EM6603 Ultra Low Power Multi I/O Microcontroller Features • Low Power - typical 1.8µA active mode - typical 0.35µA standby mode - typical 0.1µA sleep mode @ 1.5V, 32kHz, 25 °C • Low Voltage - 1.2 to 3.6 V • buzzer - three tone • ROM - 2k × 16 (Mask Programmed) • RAM - 96 × 4 (User Read/Write) • 2 clocks per instruction cycle • RISC architecture • 4 software configurable 4-bit ports • Up to 16 inputs (4 ports) • Up to 12 outputs (3 ports) • Serial (Output) Write buffer - SWB • Voltage level detection • Analogue watchdog • Timer watchdog • 8 bit timer / event counter • Internal interrupt sources (timer, event counter, prescaler, SWB) • External interrupt sources (portA + portC) Figure 1.Architecture Figure 2.Pin Configuration Description The EM6603 is an advanced single chip low cost, mask programmed - CMOS 4-bit microcontroller. It contains ROM, RAM, watchdog timer, oscillation detection circuit, combined timer / event counter, prescaler, voltage level detector and a number of clock functions. Its low voltage and low power operation make it the most suitable controller for battery, stand alone and mobile equipment. The EM66XX series is manufactured using EM Microelectronic’s Advanced Low Power CMOS Process. Typical • • • • • • • • Applications sensor interfaces domestic appliances security systems bicycle computers automotive controls TV & audio remote controls measurement equipment R/F and IR. control 03/02 REV. G/439 Copyright  2002, EM Microelectronic-Marin SA 1 www.emmicroelectronic.com EM6603 EM6603 at a glance • Power Supply - Low Voltage, low power architecture including internal voltage regulator - 1.2V ... 3.6 V battery voltage - 1.8µA in active mode - 0.35µA in standby mode - 0.1µA in sleep mode @ 1.5V, 32kHz, 25 °C - 32 kHz Oscillator • RAM - 96 x 4 bit, direct addressable • ROM - 2048 x 16 bit metal mask programmable • CPU - 4 bit RISC architecture - 2 clock cycles per instruction - 72 basic instructions • Main Operating Modes and Resets - Active mode (CPU is running) - Standby mode (CPU in Halt) - Sleep mode (No clock, Reset State) - Initial reset on Power-On (POR) - External reset pin - Watchdog timer (time-out) reset - Oscillation detection watchdog reset - Reset with input combination on PortA (metal option) • 4-Bit Input PortA - Direct input read - Debounced or direct input selectable (reg.) - Interrupt request on input’s rising or falling edge, selectable by register. - Pull-down or none, selectable by metal mask - Software test variables for conditional jumps - PA3 input for the event counter - Reset with input combination on PortA (metal option) • 4-Bit Input/Output PortB - separate input or output selection by register - Pull-up, Pull-down or none, selectable by metal mask if used as Input - Buzzer output on PB0 • 4-Bit Input/Output PortC - Input or Output port as a whole port - Debounced or direct input selectable (reg.) - Interrupt request on input’s rising or falling edge, selectable by register. - Pull-up, pull-down or none, selectable by metal mask if used as input - CMOS or N-channel open drain mode • 4-Bit Input/Output PortD - Input or Output port as a whole port - Pull-up, Pull-down or none, selectable by metal mask if used as Input - CMOS or N-channel open drain mode - Serial Write Buffer clock and data output • Serial (output) Write Buffer - max. 256 bits long clocked with 16/8/2/1kHz - automatic send mode - interactive send mode : interrupt request when buffer is empty • Buzzer Output - if used output on PB0 - 3 tone buzzer - 1kHz, 2kHz, 2.66kHz - 32kHz output possible on the STB/RST pin - 15 stage system clock divider down to 1 Hz - 3 interrupt requests : 1Hz/8Hz/32Hz - Prescaler reset (from 8kHz to 1Hz) • 8-bit Timer / Event Counter - 8-bit auto-reload count-down timer - 6 different clocks from prescaler - or event counter from the PA3 input - parallel load - interrupt request when comes to 00 hex. • Supply Voltage Level Detector - 3 software selectable levels (1.3V, 2.0V, 2.3V or user defined between 1.3V and 3.0V) - Busy flag during measure - Active only on request during measurement to reduce power consumption • Prescaler - 8 external interrupt sources: 4 from Port A and 4 from Port C - 3 internal interrupt sources, prescaler, timer and Serial Write Buffer - each interrupt request is individually maskable - interrupt request flag is cleared automatically on register read • Interrupt Controller 03/02 REV. G/439 Copyright  2002, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com EM6603 Table of Contents 1 OPERATING MODES 1.1 STANDBY MODE 1.2 SLEEP MODE 2 POWER SUPPLY 3 RESET 3.1 OSCILLATION DETECTION CIRCUIT 3.2 RESET PIN 3.3 INPUT PORT (PA0..PA3) RESET 3.4 WATCHDOG TIMER RESET 3.5 CPU STATE AFTER RESET 4 OSCILLATOR 4.1 PRESCALER 5 WATCHDOG TIMER 6 INPUT AND OUTPUT PORTS 6.1 PORTA 6.2 PORTA REGISTERS 6.3 PORTB 6.4 PORTB REGISTERS 6.5 PORTC 6.6 PORTC REGISTERS 6.7 PORTD 6.8 PORTD REGISTERS 7 BUZZER 7.1 BUZZER REGISTER 8 TIMER/EVENT COUNTER 8.1 TIMER/COUNTER REGISTERS 9 INTERRUPT CONTROLLER 9.1 INTERRUPT CONTROL REGISTERS 10 10.1 11 11.1 11.2 12 13 14 15 15 16 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 17 18 18.1 18.2 18.3 19 PERIPHERAL MEMORY MAP ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS STANDARD OPERATING CONDITIONS HANDLING PROCEDURES DC CHARACTERISTICS - POWER SUPPLY PINS DC CHARACTERISTICS - INPUT/OUTPUT PINS DC CHARACTERISTICS - SUPPLY VOLTAGE DETECTOR LEVELS OSCILLATOR INPUT TIMING CHARACTERISTICS PAD LOCATION DIAGRAM PACKAGE AND ORDERING INFORMATION ORDERING INFORMATION PACKAGE MARKING CUSTOMER MARKING SPECIFICATION CHANGE SUPPLY VOLTAGE LEVEL DETECTOR (SVLD) SVLD REGISTER SERIAL (OUTPUT) WRITE BUFFER – SWB SWB AUTOMATIC SEND MODE SWB INTERACTIVE SEND MODE STROBE / RESET OUTPUT 5 5 5 5 6 6 6 7 7 7 8 8 8 9 9 10 11 11 12 12 14 14 15 15 16 17 18 18 20 20 21 23 25 26 Table of Figures Figure 1.Architecture Figure 2.Pin Configuration Figure 3.Typical Configuration Figure 4.Mode Transition diagram Figure 5.System reset generation Figure 6.Port A Figure 7.Port B Figure 8.Port C Figure 9.Port D Figure 10.Timer / Event Counter Figure 11.Interrupt Request generation Figure 12.Serial write buffer Figure 13.Automatic Serial Write Buffer transmission Figure 14.Interactive Serial Write Buffer transmission Figure 15. EM6603 PAD Location Diagram Figure 16. Dimensions of PDIP24 Pack. - Pack. type “A” Figure 17. Dimensions of TSSOP24 Pack. - Pack. type “F” Figure 18. Dimensions of SOP24 Pack. SOIC – Pack. type “B” 1 1 4 5 6 10 11 13 14 16 19 22 23 25 34 34 35 35 Table of Tables Table 1. Pin Description Table 2.StandBy and Sleep Activities Table 3. PortA Inputs RESET options (metal Hardware option) Table 4. Watchdog-Timer Option (software option) Table 5. Initial Value After RESET Table 6.Prescaler interrupt source Table 7. Prescaler control register - PRESC Table 8.Watchdog register - WD Table 9.Input / Output Ports Overview Table 10.Option register - Option Table 11.PortA input status register - PortA Table 12.PortA Interrupt request register - IRQpA Table 13.PortA interrupt mask register - MportA Table 14.PortB input status register - PortB Table 15.PortB Input/Output control register - CIOportB Table 16.Ports A&C Interrupt Request Table 17.PortC input/output register - PortC Table 18.PortC Interrupt request register - IRQpC Table 19.PortC interrupt mask register - MportC Table 20.PortD Input/Output register - PortD Table 21.Ports control register - CPIOB Table 22.Buzzer frequency selection Table 23.Buzzer control register - BEEP Table 24.Timer Clock Selection Table 25.Timer control register - TimCtr Table 26.LOW Timer Load/Status register -LTimLS (4 low bits) Table 27.HIGH Timer Load/Status register-HTimLS (4 high bits) Table 28.PA3 counter input selection register - PA3cnt Table 29.PA3 counter input selection Table 30.Main Interrupt request register - IntRq (Read Only)* Table 31.register - CIRQD Table 32. SVLD level selection Table 33.SVLD control register - SVLD Table 34.SWB clock selection Table 35.SWB clock selection register - ClkSWB Table 36.PortD status Table 37.SWB buffer register - SWbuff Table 38.SWB Low size register - LowSWB Table 39.SWB High size register - HighSWB Table 40 Input/Output Ports Table 41 PortA RESET option Table 42 SVLD levels 4 5 7 7 7 8 8 8 9 9 10 10 10 11 11 12 12 12 12 14 14 15 15 17 17 17 17 17 17 18 19 20 20 21 21 21 22 22 22 27 27 27 TEST AT EM - ACTIVE SUPPLY CURRENT TEST 26 METAL MASK OPTIONS 27 28 28 30 30 30 30 30 31 32 33 33 34 34 36 36 36 37 03/02 REV. G/439 Copyright  2002, EM Microelectronic-Marin SA 3 www.emmicroelectronic.com EM6603 Table 1. Pin Description Pin Number Pin Name 1 port A, 0 2 port A, 1 3 port A, 2 4 port A, 3 5 port B, 0 6 port B, 1 7 port B, 2 8 port B, 3 9 test 10 Qout/osc 1 11 Qin/osc 2 12 Vss 13 STB/RST 14 port C, 0 15 port C, 1 16 port C, 2 17 port C, 3 18 port D, 0 19 port D, 1 20 port D, 2 21 port D, 3 22 reset 23 Vreg 24 Vdd Function input 0 port A input 1 port A input 2 port A input 3 port A input / output 0 port B input / output 1 port B input / output 2 port B input / output 3 port B test input terminal crystal terminal 1 crystal terminal 2 (input) negative power supply terminal strobe / reset status input / output 0 port C input / output 1 port C input / output 2 port C input / output 3 port C input / output 0 port D input / output 1 port D input / output 2 port D input / output 3 port D reset terminal internal voltage regulator positive power supply terminal Remarks interrupt request; interrupt request; interrupt request; interrupt request; buzzer output tvar 1 tvar 2 tvar 3 event counter input for EM test purpose only (internal pull-down) Can accept trimming capacitor tw. Vss µC reset state + port B, C, D write interrupt request interrupt request interrupt request interrupt request SWB Serial Clock Output SWB Serial Data Outp