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EM MICROELECTRONIC - MARIN SA
EM6520
MFP version of EM6620 Ultra Low Power Microcontroller 4x8 LCD Driver
Features
• Low Power - 8 µA active mode, LCD On - 1.1 µA standby mode, LCD Off - 0.1 µA sleep mode @ 3 V, 32 kHz, 25°C Large Voltage range, 2 to 5.5 V SVLD, default (2.4V) EEPROM, 2048 × 16 bits RAM, 64 × 4 bits 2 clocks per instruction cycle 72 basic instructions Oscillation supervisor Timer watchdog (2 sec) Max. 8 inputs ; port A, port B max. 4 outputs ; port B LCD 8 segments, 3 or 4 times multiplexed Universal 10-bit counter, PWM, event counter Prescaler down to 1 Hz (crystal = 32 KHz) 1/1000 sec, 12 bit binary coded decimal counter with hard or software start/stop function Frequency output 1Hz, 2048 Hz, 32 KHz, PWM 7 internal interrupt sources (BCD counter, 2×10-bit counter, 3× prescaler, SVLD) 5 external interrupt sources (port A, compare) Figure 1. Architecture
• • • • • • • • • • • • • • • • • •
Description
The EM6520 is an advanced single chip CMOS 4bit microcontroller. It contains EEPROM, RAM, power on reset, watchdog timer, oscillation detection circuit, 10 bit up/down counter, Millisecond counter, prescaler, voltage level detector (SVLD), compare input, frequency output, LCD driver and several clock functions. The low voltage feature and low power consumption make it the most suitable controller for battery, stand alone and mobile equipment. The EM6520 is manufactured using EM Microelectronic’s Advanced Low Power (ALP) CMOS Process. Figure 2. Pin Configuration
Typical Applications
• • • • • • • • • Timing device Medical applications Domestic appliance Timer / sports timing devices Safety and security devices Automotive controls with display Measurement equipment Interactive system with display Bicycle computers
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EM6520
EM6520 at a glance
• Power Supply - Low voltage low power architecture including internal voltage regulator - 2.0 ... 5.5 V battery voltage - 8 µA in active mode (Xtal, LCD on, 25°C) - 1.1 µA in standby mode (Xtal, LCD off, 25°C) - 0.1 µA in sleep mode (25°C) - 32 KHz Oscillator • Prescaler - 15 stage system clock divider down to 1Hz - 3 Interrupt requests; 1Hz, 32Hz or 8Hz, Blink - Prescaler reset (4kHz to 1Hz)
• 4-Bit Bi-directional Port B - All different functions bit-wise selectable
• •
RAM EEPROM
- 64 x 4 bit, direct addressable
- 2048 x 16 bits programmable with EM’s standard MFP programming box
- Direct input read on the port terminals - Data output latches - CMOS or Nch. open drain outputs - Pull-down or pull-up selectable - Pull-up in Nch. open drain mode - Selectable PWM, 32kHz, 1kHz and 1Hz output - Dynamic Input Comparator on PB[0] (SVLD level) • Voltage Level Detector - Default value 2.4V - Busy flag during measure - Interrupt request at end of measure
•
•
CPU
- 4 bit RISC architecture - 2 clock cycles per instruction - 72 basic instructions • Main Operating Modes and Resets - Active Mode (CPU is running) - Standby Mode (CPU in halt) - Sleep Mode (no clock, reset state) - Initial reset on power on (POR) - Watchdog reset (logic and oscillation watchdogs) - Reset with input combination on port A (register selectable) • Liquid Crystal Display Driver - 8 segments 3 or 4 times multiplexed - Internal or external voltage multiplier - Free segment allocation architecture (metal 2 mask) - LCD switch off for power save
10-Bit Universal Counter
- 10, 8, 6 or 4 bit up/down counting - Parallel load - Event counting (PA[0] or PA[3]) - 8 different input clocks- Full 10 bit or limited (8, 6, 4 bit) compare function - 2 interrupt requests (on compare and on 0) - Hi-frequency input on PA[3] and PA[0] - Pulse width modulation (PWM) output
•
(LCD)
Millisecond Counter
- 3 digits binary coded decimal counter (12 bits) - PA[3] signal pulse width and period measurement - Internal 1000 Hz clock generation - Hardware or software controlled start stop mode - Interrupt request on either 1/10 Sec or 1Sec • Interrupt Controller - 5 external and 7 internal interrupt request sources - Each interrupt request individually maskable - Each interrupt flag individually resettable - Automatic reset of each interrupt request register after read - General interrupt request to CPU can be disabled - Automatic enabling of general interrupt request flag when going into HALT mode
• 4-Bit Input Port A - Direct input read on the port terminals - Debouncer function available on all inputs - Interrupt request on positive or negative edge - Pull resistor selectable by register - Test variables (software) for conditional jumps - PA[0] and PA[3] are inputs for the event counter - PA[3] is Start/Stop input for the millisecond counter - Reset with input combination (register selectable)
03/02 REV. D/449
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EM6520
Table of Contents
Features Description Typical Applications EM6520 at a glance 1 2 Pin Description for EM6520 1.1 Programming Connections Operating modes 2.1 ACTIVE Mode 2.2 STANDBY Mode 2.3 SLEEP Mode Power Supply Reset 4.1 Oscillation Detection Circuit 4.2 Input Port A Reset 4.3 Digital Watchdog Timer Reset 4.4 CPU State after Reset Oscillator and Prescaler 5.1 Oscillator 5.2 Prescaler Input and Output ports 6.1 Ports overview 6.2 Port A
6.2.1 6.2.2 6.2.3 6.2.4 IRQ on Port A Pull-up/down Software test variables Port A for 10-Bit Counter and MSC
1 1 1 2 4 5 6 6 6 6 7 8 9 9 10 10 11 11 11 13 13 14
14 15 15 15
8.2 8.3 8.4 8.5 9
IRQ from MSC MSC-Modes Mode selection Millisecond Counter Registers
27 28 28 30 31 32 33 33 34 35 36 36 37 37 39 42 43 44 44
44 45 46 46 46 46
Interrupt Controller 9.1 Interrupt control registers
10 Supply Voltage Level Detector 10.1 SVLD Register 11 RAM
3 4
12 LCD Driver 12.1 LCD Control 12.2 LCD addressing 12.3 Free segment allocation 12.4 LCD Registers 13 14 15 PERIPHERAL MEMORY MAP Option Register Memory Map Active Supply Current test
5
16 Mask Options 16.1 Input / Output Ports
16.1.1 16.1.2 16.1.3 16.1.4 16.1.5 16.1.6 Port A Metal Options Port B Metal Options Voltage Regulator Option SVLD and Input Comp Level Option Debouncer frequency Option User defined LCD Segment allocation
6
6.3 6.4
6.4.1 6.4.2 6.4.3 6.4.4
Port A registers Port B
Input / Output Mode Pull-up/Down CMOS / NCH. Open Drain Output PWM and Frequency output
15 17
17 18 18 19
17 Measured Electrical Behaviors 17.1 IDD Current 17.2 Regulator Voltage 17.3 Pull Resistors 17.4 Output currents 18 EM6520 Electrical specifications 18.1 Absolute maximum ratings 18.2 Handling Procedures 18.3 Standard Operating Conditions 18.4 DC characteristics - Power Supply 18.5 SVLD and Input Comparator 18.6 Oscillator 18.7 DC characteristics - I/O Pins 18.8 LCD Seg[8:1] Outputs 18.9 LCD Com[4:1] Outputs 18.10 DC Output Component 18.11 LCD voltage multiplier 19 Pad Location Diagram
47 47 47 47 48 49 49 49 49 49 50 50 51 52 52 52 52 53 54 54
6.5 6.6 7
PB[0] Dynamic Input Comparator Port B registers
19 20 21 21 22 23 23 23
24 24
10-bit Counter 7.1 Full and Limited Bit Counting 7.2 Frequency Select and Up/Down Counting 7.3 Event Counting 7.4 Compare Function 7.5 Pulse Width Modulation (PWM)
7.5.1 7.5.2 How the PWM Generator works. PWM Characteristics
7.6 7.7 8
Counter Setup 10-bit Counter Registers
25 25 27 27
Millisecond Counter 8.1 PA[3] Input for MSC
20 Package & Ordering Information 20.1 Ordering Information
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
03/02 REV. D/449
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EM6520
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Pin Description for EM6520
44 DIL 40 QFP 32
Chip QFP 13 14 15 16 18 19 20 21 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 43 1 2 3 5 6 8 10 11
7 8 9 10 11 12 13 14 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 35 36 37 38 39 40 1 3 5
9 10 11 12 13 14 15 16 17 18 19 nc 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
Signal Name C2B C2A C1B C1A VL1 VL2 VL3 COM[4] COM[3] COM[2] COM[1] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] SEG[1] Test PB[0] PB[1] PB[2] PB[3] PA[0] PA[1] PA[2] PA[3] VBAT=VDD Vreg Qout / Osc2 Qin / Osc1 VSS
Function Voltage multiplier Voltage multiplier Voltage multiplier Voltage multiplier Voltage multiplier level 1 Voltage multiplier level 2 Voltage multiplier level 3 LCD back plane 4 LCD back plane 3 LCD back plane 2 LCD back plane 1 LCD segment 8 LCD segment 7 LCD segment 6 LCD segment 5 LCD segment 4 LCD segment 3 LCD segment 2 LCD segment 1 Input test terminal Internal pull-down 15k Input/output, open drain port B terminal 0 Input/output, open drain port B terminal 1 Input/output, open drain port B terminal 2 Input/output, open drain port B terminal 3 Input port A terminal 0 Input port A terminal 1 Input port A terminal 2 Input port A terminal 3 Positive power supply Internal voltage regulator Crystal terminal Crystal terminal Negative power supply
Remarks Not needed if ext. supply Not needed if ext. supply Not needed if ext. supply Not needed if ext. supply LCD level 1 input, if external supply selected LCD level 2 input, if external supply selected LCD level 3 input, if external supply selected Not used if 3 times multiplex selected
Not bonded for QFP 32
For EM tests only, GND 0 ! except when needed for MFP programming Port B data[0] I/O or dynamic input comparator input Port B data[1] I/O or ck[12] output Port B data[2] I/O or ck[1] output Port B data[3] I/O or PWM
