2M x 32 Synchronous DRAM

EtronTech Features Clock rate: 200/183/166/143/125/100 MHz Fully synchronous operation Internal pipelined architecture Four internal banks (512K x 32bit x 4bank) Programmable Mode - CAS# Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst-Read-Single-Write • Burst stop function • Individual byte controlled by DQM0-3 • Auto Refresh and Self Refresh • 4096 refresh cycles/64ms • Single +3.3V ± 0.3V power supply • Interface: LVTTL • Package: 400 x 875 mil, 86 Pin TSOP II, 0.50mm pin pitch Lead Free Package available • • • • • • EM638325 2M x 32 Synchronous DRAM (SDRAM) Preliminary (Rev 1.4 October/2005) Pin Assignment (Top View) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /WE /CAS /RAS /CS NC BS0 BS1 A10/AP A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS Ordering Information Part Number Leaded / Lead Free Package EM638325TS-5/-5G EM638325TS-5.5/-5.5G EM638325TS-6/-6G EM638325TS-7/-7G EM638325TS-8/-8G EM638325TS-10/-10G 200MHz 183MHz 166MHz 143MHz 125MHz 100MHz TSOP II TSOP II TSOP II TSOP II TSOP II TSOP II Frequency Package Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech Overview 2Mega x 32 SDRAM EM638325 The EM638325 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM638325 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth. Block Diagram Col um n Row Decoder De co der 2048 X 256 X 32 CELL ARRAY (BANK #0) Sense Ampl ifier CL K DLL CL OCK B U FFER CON TRO L SI G N A L GEN ER A TO R Sense Row Decoder CK E Ampl ifier C S# R A S# C A S# W E# COMMAND D E C O D ER M OD E R EG I ST ER 2048 X 256 X 32 CELL ARRAY (BANK #1) Col um n De coder CO LU MN C OU N T ER A 10/A P Col um n Row Decoder De co der A0 A9 B S0 B S1 A D D R E SS B U FFER 2048 X 256 X 32 CELL ARRAY (BANK #2) Sense Ampl ifier R E F R E SH C O U N TER Sense DQ B U FFER D Q0 │ D Q31 Row Decoder Ampl ifier 2048 X 256 X 32 CELL ARRAY (BANK #3) Col um n De co der D QM 0~3 Preliminary 2 Rev 1.4 Oct. 2005 EtronTech Pin Descriptions 2Mega x 32 SDRAM EM638325 Table 1. Pin Details of EM638325 Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low standby power. Input Bank Select: BS0 and BS1 defines to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. BS is also used to program the 11th bit of the Mode and Special Mode registers. CKE BS0, BS1 A0-A10 Input Address Inputs: A0-A10 are sampled during the BankActivate command (row address A0A10) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one location out of the 256K available in the respective bank. During a Precharge command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH). The address inputs also provide the op-code during a Mode Register Set or Special Mode Register Set command. CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. Input Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. Input Column Address Strobe: The CAS# signal conjunction with the RAS# and WE# signals and When RAS# is held "HIGH" and CS# is asserted asserting CAS# "LOW." Then, the Read or Write "LOW" or "HIGH." defines the operation commands in is latched at the positive edges of CLK. "LOW," the column access is started by command is selected by asserting WE# RAS# CAS# WE# Input Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. DQM0 - Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer controls. DQM3 The I/O buffers are placed in a high-z state when DQM is sampled HIGH. Input data is masked when DQM is sampled HIGH during a write cycle. Output data is masked (twoclock latency) when DQM is sampled HIGH during a read cycle. DQM3 masks DQ31DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0. DQ0- Input/ Data I/O: The DQ0-31 input and output data are synchronized with the positive edges of DQ31 Output CLK. The I/Os are byte-maskable during Reads and Writes. Preliminary 3 Rev 1.4 Oct. 2005 EtronTech NC VDDQ VSSQ VDD VSS Supply Power Supply: +3.3V±0.3V Supply Ground 2Mega x 32 SDRAM EM638325 No Connect: These pins should be left unconnected. Supply DQ Power: Provide isolated power to DQs for improved noise immunity. Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. Preliminary 4 Rev 1.4 Oct. 2005 EtronTech Operation Mode 2Mega x 32 SDRAM EM638325 Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode Register Set No-Operation Burst Stop Device Deselect AutoRefresh SelfRefresh Entry SelfRefresh Exit State Idle(3) Any Any Active(3) Active(3) Active(3) Active(3) Idle Any Active(4) Any Idle Idle Idle (SelfRefresh) CKEn-1 CKEn DQM(6) BS0,1 A10 H H H H H H H H H H H H H L H H L L H X X X X X X X X X X X H L H L L H H X X X X X X X X X X X X X X X X X X X L X X X X X X X X X X X V V X V V V V L H L H L H A9-0 X X Column address (A0 ~ A7) Column address (A0 ~ A7) CS# RAS# CAS# WE# L L L L L L L L L L L H H H H L H H X L L X H X X H X X H X H H H L L L L L H H X L L X H X X H X X H X H L L L L H H L H L X H H X H X X H X X H X X Row address OP code X X X X X X X X X X X X X X X X X X X X X X L L H L L H L X H L X H L X Clock Suspend Mode Entry Power Down Mode Entry Active Any(5) Active Any (PowerDown) Clock Suspend Mode Exit Power Down Mode Exit Data Write/Output Enable Data Mask/Output Disable Active Active H X H X X X X X X Note: 1. V = Valid, X = Don't care, L = Logic low, H = Logic high 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode. 6. DQM0-3 Preliminary 5 Rev 1.4 Oct. 2005 EtronTech Commands 1 2Mega x 32 SDRAM EM638325 BankActivate (RAS# = "L", CAS# = "H", WE# = "H", BS = Bank, A0-A10 = Row Address) The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal. By latching the row address on A0 to A10 at the time of this command, the sel