1Mega x 16 Synchronous DRAM

EtronTech Features • • • • • • Fast access time: 5/5.5/6.5/7.5 ns Fast clock rate: 166/143/125/100 MHz Self refresh mode: standard and low power Internal pipelined architecture 512K word x 16-bit x 2-bank Programmable Mode registers - CAS# Latency: 1, 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function Individual byte controlled by LDQM and UDQM Auto Refresh and Self Refresh 4096 refresh cycles/64ms CKE power down mode Single +3.3V±0.3V power supply Interface: LVTTL 50-pin 400 mil plastic TSOP II package Lead Free Package available EM636165-XXI Preliminary (Rev. 1.1, 04/2005) 1Mega x 16 Synchronous DRAM (SDRAM) Pin Assignment (Top View) VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE# CAS# RAS# CS# A11 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Vss DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 Vss • • • • • • • • Key Specifications EM636165 tCK3 tRAS tAC3 tRC Clock Cycle time(min.) Row Active time(max.) Access time from CLK(max.) Row Cycle time(min.) -6I/7I/8I/10I 6/7/8/10ns 36/42/48/60 ns 5/5.5/6.5/7.5 ns 54/63/72/90 ns Ordering Information Industrial Operating temperature: -40~85°C Part Number EM636165TS-6I/6IG EM636165TS-7I/7IG EM636165TS-8I/8IG Frequency 166MHz 143MHz 125MHz Package TSOP II TSOP II TSOP II TSOP II EM636165TS-10I/10IG 100MHz G : indicates Lead Free Package Overview The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These Etron Technology, Inc. No. 6, Technology Road V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech Block Diagram EM636165-XXI devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications CLK CLOCK BUFFER Row Decoder Column Decoder 2048 X 256 X 16 CELL ARRAY (BANK #0) Sense Amplifier CKE CS# RAS# CAS# WE# LDQM UDQM COMMAND DECODER CONTROL SIGNAL GENERATOR COLUMN COUNTER DQs Buffer DQ0 │ DQ15 A0 A11 ADDRESS BUFFER MODE REGISTER Sense Amplifier REFRESH COUNTER Row Decoder 2048 X 256 X 16 CELL ARRAY (BANK #1) Column Decoder Preliminary 2 Rev. 1.1 Apr. 2005 EtronTech Pin Descriptions Symbol CLK Type Input 1M x 16 SDRAM EM636165-XXI Table 1. Pin Details of EM636165 Description Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When both banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low standby power. Bank Select: A11(BS) defines to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. Address Inputs: A0-A10 are sampled during the BankActivate command (row address A0-A10) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one location out of the 256K available in the respective bank. During a Precharge command, A10 is sampled to determine if both banks are to be precharged (A10 = HIGH). The address inputs also provide the op-code during a Mode Register Set command. Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. Column Address Strobe: The CAS# signal defines the operation commands in conjunction with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS# "LOW." Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH." Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. CKE Input A11 A0-A10 Input Input CS# Input RAS# Input CAS# Input WE# Input Preliminary 3 Rev. 1.1 Apr. 2005 EtronTech LDQM, UDQM Input 1M x 16 SDRAM EM636165-XXI Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent I/O buffer controls. The I/O buffers are placed in a high-z state when LDQM/UDQM is sampled HIGH. Input data is masked when LDQM/UDQM is sampled HIGH during a write cycle. Output data is masked (two-clock latency) when LDQM/UDQM is sampled HIGH during a read cycle. UDQM masks DQ15DQ8, and LDQM masks DQ7-DQ0. DQ0-DQ15 Input/Output Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os are byte-maskable during Reads and Writes. NC VDDQ Supply No Connect: These pins should be left unconnected. DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V± 0.3V ) VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. (0V) VDD VSS Supply Supply Power Supply: +3.3V ± 0.3V Ground Preliminary 4 Rev. 1.1 Apr. 2005 EtronTech Operation Mode 1M x 16 SDRAM EM636165-XXI Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode Register Set No-Operation Burst Stop Device Deselect AutoRefresh SelfRefresh Entry SelfRefresh Exit State Idle(3) Any Any Active(3) Active(3) Active(3) Active(3) Idle Any Active(4) Any Idle Idle Idle (SelfRefresh) CKEn-1 CKEn DQM(6) A11 A10 A0-9 CS# RAS# CAS# WE# H H H H H H H H H H H H H L H H L L H X X X X X X X X X X X H L H L L H H X X X X X X X X X X X X X X X X X X X L V V X V V V V V X X X X X X X X X X X V L H L H L H V X X X X X X X X X X X V X X V V V V V X X X X X X X X X X X L L L L L L L L L L H L L H L X H L X H L X L L L H H H H L H H X L L X H X X H X X H X H H H L L L L L H H X L L X H X X H X X H X H L L L L H H L H L X H H X H X X H X X H X X Clock Suspend Mode Entry Power Down Mode Entry Active Any(5) Active Any (PowerDown) Clock Suspend Mode Exit Power Down Mode Exit Data Write/Output Enable Data Mask/Output Disable Active H X H X X X X X X Active Note: 1. V=Valid X=Don't Care L=Low level H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode. 6. LDQM and UDQM Preliminary 5 Rev. 1.1 Apr. 2005 EtronTech Commands 1 1M x 16 SDRAM EM636165-XXI BankPrecharge command (RAS# = "L", CAS# = "H", WE# = "L", A11 = “V”, A10 = "L", A0-A9 = Don't care) The BankPrecharge command precharges the bank disignated by A11 signal. The precharged bank is switched from the active state to the idle state. This command can be asserted anytime after tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. PrechargeAll command (RAS# = "L",