Synchronous DRAM

www.DataSheet4U.com eorex Features EM488M3244VBA 256Mb (2M×4Bank×32) Synchronous DRAM Description The EM488M3244VBA is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 256Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL. Available packages: TFBGA-90B(13mmx8mm). • Fully Synchronous to Positive Clock Edge • Single 3.3V ±0.3V Power Supply • LVTTL Compatible with Multiplexed Address • Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page • Programmable CAS Latency (C/L) - 2 or 3 • Data Mask (DQM) for Read / Write Masking • Programmable Wrap Sequence – Sequential (B/L = 1/2/4/8/full Page) – Interleave (B/L = 1/2/4/8) • Burst Read with Single-bit Write Operation • All Inputs are Sampled at the Rising Edge of the System Clock • Auto Refresh and Self Refresh • 4,096 Refresh Cycles / 64ms (15.625us) Ordering Information Part No EM488M3244VBA-75F Organization 8M X 32 Max. Freq 133MHz @CL3 Package TFBGA -90B Grade Commercial Pb Free * EOREX reserves the right to change products or specification without notice. Jul. 2006 1/17 www.eorex.com eorex Pin Assignment 1 DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 2 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS 3 A B C D E F G H J K L M N P R VDD EM488M3244VBA 7 DQ23 8 DQ21 DQ19 9 VDDQ DQ22 DQ17 NC A2 A10 NC BA0 /CAS VDD DQ6 DQ1 VDDQ VDD VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 /CS /WE DQ7 DQ5 DQ3 VSSQ DQ0 VDDQ VDDQ VSSQ VDD A1 A11 /RAS DQM0 VSSQ VDDQ VDDQ DQ4 DQ2 90ball TFBGA / (13mm x 8mm) Jul. 2006 2/17 www.eorex.com eorex Pin Description (Simplified) Pin J1 J8 Name CLK /CS EM488M3244VBA Function (System Clock) Master clock input (Active on the positive rising edge) (Chip Select) Selects chip when active (Clock Enable) Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. (Address) Row address (A0 to A11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. CA (CA0 to CA8) is determined by A0 to A8 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10= High at the pre-charge command cycle, all banks are pre-charged. But when A10= Low at the pre-charge command cycle, only the bank that is selected by BA is pre-charged. (Bank Address) Selects which bank is to be active. (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Data Input/Output Mask) DQM controls I/O buffers. J2 CKE G8,G9,F7,F3,G1, G2,G3,H1,H2,J3, G7,H9 A0~A11 J7,H8 J9 BA0,BA1 /RAS K7 /CAS K8 K9,K1,F8,F2 R8,N7,R9,N8,P9, M8,M7,L8,L2,M3, M2,P1,N2,R1,N3, R2,E8,D7,D8,B9, C8,A9,C7,A8,A2, C3,A1,C2,B1,D2, D3,E2 A7,F9,L7,R7/ A3,F1,L3,R3 B2,B7,C9,D9,E1, L1,M9,N9,P2/B8, B3,C1,D1,E9,L9, M1,N1,P8 E3,E7,H3,H7,K2, K3 Jul. 2006 /WE DQM0~DQM3 DQ0~DQ31 (Data Input/Output) DQ pins have the same function as I/O pins on a conventional DRAM. VDD/VSS (Power Supply/Ground) VDD and VSS are power supply pins for internal circuits. (Power Supply/Ground) VDDQ and VSSQ are power supply pins for the output buffers. (No Connection) This pin is recommended to be left No Connection on the device. www.eorex.com 3/17 VDDQ/VSSQ NC eorex Absolute Maximum Rating Symbol VIN, VOUT VDD, VDDQ TOP TSTG PD IOS Item Input, Output Voltage Power Supply Voltage Operating Temperature Range Storage Temperature Range Power Dissipation Short Circuit Current EM488M3244VBA Rating -0.5 ~ +4.6 -0.5 ~ +4.6 Commercial 0 ~ +70 Extended -25 ~ +85 -55 ~ +150 1 50 Units V V °C °C W mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (VCC=3.3V, f=1MHz, TA=25°C) Symbol CCLK CI CO Parameter Clock Capacitance Input Capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML, DQMU Input/Output Capacitance Min. 1.5 1.5 3.0 Typ. Max. 3.0 3.0 5.5 Units pF pF pF Recommended DC Operating Conditions (TA=0°C ~70°C) Symbol VDD VDDQ VIH VIL Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input Logic High Voltage Input Logic Low Voltage Min. 3.0 3.0 2.0 -0.3 Typ. 3.3 3.3 Max. 3.6 3.6 VDD+0.3 0.8 Units V V V V Note: * All voltages referred to VSS. * VIH (max.) = VDD+1.5V for pulse width 5ns * VIL (min.) = VSS-1.5V for pulse width 5ns Jul. 2006 4/17 www.eorex.com eorex Recommended DC Operating Conditions (VDD=3.3V±0.3V, TA=0°C ~70°C) Symbol ICC1 ICC2P ICC2PS ICC2N Parameter Operating Current (Note 1) EM488M3244VBA Test Conditions Burst length=1, tRC≥tRC(min.), IOL=0mA, One bank active CKE≤VIL(max.), tCK=15ns CKE≤VIL(max.), tCK= ∞ CKE≥VIL(min.), tCK=15ns, /CS≥VIH(min.) Input signals are changed one time during 30ns CKE≥VIL(min.), tCK= ∞ , Input signals are stable CKE≤VIL(max.), tCK=15ns CKE≤VIL(max.), tCK= ∞ CKE≥VIL(min.), tCK=15ns, /CS≥VIH(min.) Input signals are changed one time during 30ns CKE≥VIL(min.), tCK= ∞ , Input signals are stable tCCD≥2CLKs, IOL=0mA tRC≥tRC(min.) CKE≤0.2V 3 Max. 125 3 2 20 Units mA mA mA mA Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-power Down Mode ICC2NS ICC3P ICC3PS ICC3N Active Standby Current in Power Down Mode 9 4 3 45 mA mA mA mA Active Standby Current in Non-power Down Mode ICC3NS ICC4 ICC5 ICC6 Operating Current (Burst Mode) (Note 2) (Note 3) 30 150 270 (Note 4) mA mA mA mA Refresh Current Self Refresh Current *All voltages referenced to VSS. Note 1: ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during t CK (min.) Note 2: ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during t CK (min.) Note 3: Input signals are changed only one time during t CK (min.) Note 4: Standard power version. Recommended DC Operating Conditions (Continued) Symbol IIL IOL VOH VOL Jul. 2006 5/17 Parameter Input Leakage Current Output Leakage Current High Level Output Voltage Low Level Output Voltage Test Conditions 0≤VI≤VDDQ, VDDQ=VDD All other pins not under test=0V 0≤VO≤VDDQ, DOUT is disabled I O=-2mA IO=+2mA Min. -1 -1.5 2.4 Typ. Max. +1 +1.5 0.4 Units uA uA V V www.eorex.com eorex Block Diagram Auto/Self Refresh Counter EM488M3244VBA A0 A1 A2 A3 Row Add. Buffer A4 A5 A6 A7 A8 A9 A10 A11 Address Register Row Decoder DQM Memory Array Write DQM Control Data In S/A & I/O Gating Col. Decoder Data Out DOi BA0 BA1 Col. Add. Buffer Read DQM Control Mode Register Set Col. Add. Counter Burst Counter Timing Register CLK CKE /CS /RAS /CAS /WE DQM Jul. 2006 6/17 www.eorex.com eorex AC Operating Test Conditions (VDD=3.3V±0.3V, TA=0°C ~70°C) Item Output Reference Level Output Load Input Signal Level Transition Time of Input Signals Input Reference Level EM488M3244VBA Conditions 1.4V/1.4V See diagram as below 2.4V/0.4V 2ns 1.4V AC Operating Test Characteristics (VDD=3.3V±0.3V, TA=0°C ~70°C) Symbol tCK tAC tCH tCL tOH tHZ tLZ tIH tIS Parameter Clock Cycle Time Access Time form CLK CLK High Level Width CLK Low Level Width Data-out Hold Time Data-out High Impedance Time (Note 5) CL=3 CL=2 CL=3 CL=2 Min. 7 10 -75 Max. Units ns 5.4 5.4 2.5 2.5 ns ns ns ns CL=3 CL=2 CL=3 CL=2 2 2 5.4 5.4 0 0.8 1.5 ns ns ns ns Data-out Low Impedance Time Input Hold Time Input Setup Time * All voltages referenced to VSS. Note 5: tHZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. Jul. 2006 7/17 www.eorex.com eorex (VDD=3.3V±0.3V, TA=0°C ~70°C) Symbol tRC tRAS tRP tRCD tRRD tCCD tDPL tBDL tROH tREF Parameter ACTIVE to ACTIVE Command (Note 6) Period ACTIVE to PRECHARGE (Note 6) Command Period PRECHARGE to ACTIVE (Note 6) Command Period ACTIVE to READ/WRITE Delay (Note 6) Time ACTIVE(one) to ACTIVE(another) (Note 6) Command READ/WRITE Command to READ/WRITE Command Date-in to PRECHARGE Command Date-in to BURST Stop Command Data-out to High CL=3 Impedance from CL=2 PRECHARGE Command Refresh Time (4,096 cycle) -75 Min. Max. 67.5 45 20 20 15 1 2 1 3 2 64 120k EM488M3244VBA AC Operating Test Characteristics (Continued) Units ns ns ns ns ns CLK CLK CLK CLK ms * All voltages referenced to VSS. Note 6: These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole number) Recommended Power On and Initialization The following power on and initialization sequence guarantees the device is preconditioned to each user ’s specific needs. (Like a conventional DRAM) During power on, all V DD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not e