64Mb SDRAM

www.DataSheet4U.com 64Mb SDRAM Ordering Information EM 48 2M 32 4 4 V T A – 5 L EOREX Logo EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : 40 41 42 43 46 48 F: PB free package Power Blank : Standard L : Low power I : Industrial Density 16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit Organization 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32 Refresh 1 : 1K, 8 : 8K 2 : 2K, 6 :16K 4 : 4K Bank 2 : 2Bank 6 : 16Bank 4 : 4Bank 3 : 32Bank 8 : 8Bank Min Cycle Time ( Max Freq.) -5 : 5ns ( 200MHz ) -6 : 5ns ( 167MHz ) -7 : 7ns ( 143MHz ) -75 : 7.5ns ( 133MHz ) -8 : 8ns ( 125MHz ) -10 : 10ns ( 100MHz ) Revision A : 1st B : 2nd C : 3rd D :4th G: for VGA version only Interface V: 3.3V R: 2.5V Package C: CSP B: uBGA T: TSOP Q: TQFP P: PQFP ( QFP ) L: LQFP URL: http://www.eorex.com Email: sales@eorex.com Rev.01 1/33 64Mb SDRAM 64Mb( 4Banks ) Synchronous DRAM EM482M3244VTA (2Mx32) Description The EM482M3244VTA is Synchronous Dynamic Random Access Memory ( SDRAM ) organized as 524,288 words x 4 banks x 32 bits. All inputs and outputs are synchronized with the positive edge of the clock . The 64Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate in 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL . Features • Fully synchronous to positive clock edge • Single 3.3V +/- 0.3V power supply • LVTTL compatible with multiplexed address • Programmable Burst Length ( B/ L ) - 1,2,4,8 or full page • Programmable CAS Latency ( C/ L ) - 2 or 3 • Data Mask ( DQM ) for Read/Write masking • Programmable wrap sequential - Sequential ( B/ L = 1/2/4/8/full page ) - Interleave ( B/ L = 1/2/4/8 ) • Burst read with single-bit write operation • All inputs are sampled at the positive rising edge of the system clock. • Auto refresh and self refresh • 4,096 refresh cycles / 64ms * EOREX reserves the right to change products or specification without notice. Rev.01 2/33 64Mb SDRAM Pin Assignment ( Top View ) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS 86pin TSOP-II (400mil x 875 mil) (0.5mm Pin pitch) Rev.01 3/33 64Mb SDRAM Pin Descriptions ( Simplified ) Pin CLK /CS CKE Name System Clock Chip select Clock Enable Pin Function Master Clock Input(Active on the Positive rising edge) Selects chip when active Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row address (A0 to A10) is determined by A0 to A10 level at the bank active command cycle CLK rising edge. CA(CA0 to CA7) is determined by A0 to A7 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10 = High at the pre-charge command cycle, all banks are pre-charged. But when A10 = Low at the pre-charge command cycle, only the bank that is selected by BA is pre-charged. Selects which bank is to be active. A0 ~ A10 Address BA0~BA1 Bank Address /RAS Row address strobe Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. /CAS Column address strobe /WE Write Enable DQM0 ~ DQM3 Data input/output Mask DQM controls I/O buffers. DQ0 ~ 31 Data input/output DQ pins have the same function as I/O pins on a conventional DRAM. VDD/VSS VDDQ/VSSQ NC Power supply/Ground Power supply/Ground No connection VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. This pin is recommended to be left No Connection on the device. Rev.01 4/33 64Mb SDRAM Block Diagram A0 A1 A2 A3 Row Add. Buffer Auto/Self Refresh Counter DQM Row Decoder A4 A5 A6 A7 A8 A9 A10 BA0 BA1 Address Register Memory Array Write DQM Control Data In S/A & I/O gating Col. Decoder Data Out DQi Col. Add. Buffer Read DQM Control Mode Register Set Col. Add. Counter DQM /WE DQM Burst Counter Timing Register CLK /CLK CKE /CS /RAS /CAS Rev.01 5/33 64Mb SDRAM Commands Mode register set command ( /CS, /RAS, / CAS, /WE = Low ) CLK /CS /RAS /CAS /WE BA A10 CKE Add ‘H’ The EM482M3244VTA have a mode register that defines how the device operates. In this command, A0 through BA are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. The EO482M3244VTA, cannot accept any other commands,only during 2CLK can following this command. ( Figure. 1 Mode register set command ) Active command ( /CS, /RAS = Low , /CAS, /WE = High ) CLK /CS /RAS /CAS /WE BA A10 CKE Add ‘H’ Row Row The EM482M3244VTA have 4 banks, each with 2,048 rows. This command activates the bank selected by BA and a row address selected by A0 through A10.This command corresponds to a conventional DRAM’s /RAS falling. ( Figure. 2 Row address strobe and bank activate command ) Rev.01 6/33 64Mb SDRAM Precharge command ( /CS, /RAS, /WE = Low , / CAS = High ) CLK /CS /RAS /CAS /WE BA A10 CKE Add ‘H’ This command begins precharge operation of the bank selected by. When A10 is high,all banks are precharged, regardless of. When BA is low,only the bank selected by BA is precharged. ( Figure. 3 Precharged command ) Write command ( /CS, /CAS, /WE = Low, /RAS = High ) CLK /CS /RAS /CAS /WE BA A10 CKE Add ‘H’ Column If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst mode can input with this command with subsequent data on following clicks. ( Figure. 4 Column address and write command ) Rev.01 7/33 64Mb SDRAM Read command ( /CS, /CAS = Low , / RAS, /WE = High ) CLK /CS /RAS /CAS /WE BA A10 CKE Add ‘H’ Column Raed data is available after /CAS latency requirements have been met. This command sets the burst start address given by the column. ( Figure. 5 Column address and read command ) Auto refresh command ( /CS, /RAS, /CAS = Low, /WE, CKE = High ) CLK /CS /RAS /CAS /WE BA A10 CKE Add ‘H’ This command is a request to begin the CBR refresh operation. The refresh address is generated internally. Before Executing CBR refresh, all banks must be precharged. After this cycle, all banks will be in the idle (Precharged ) state and ready for a row activate command. During tRC period ( from refresh command to refresh or activate command ), the EM482M3244VTA cannot accept any other command. ( Figure. 6 Auto refresh command ) Rev.01 8/33 64Mb SDRAM Self refresh entry command ( /CS, / RAS , /CAS, CKE = Low , /WE = High ) CLK /CS /RAS /CAS /WE BA A10 CKE Add After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the memory exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there before is no need for external control. Before executing self refresh, both banks must be precharged. ( Figure. 7 Self refresh entry command ) Burst stop command ( /CS, /WE = Low, /RAS, /CAS = High ) CLK /CS /RAS /CAS /WE BA A10 CKE Add ‘H’ This command can stop the current burst operation. ( Figure. 8 Burst stop command in full page mode ) Rev.01 9/33 64Mb SDRAM No operation ( /CS = Low, / RAS , /CAS, /WE = High ) CLK /CS /RAS /CAS /WE BA A10 CKE Add ‘H‘ This command is not execution command so there is no operations begin or terminate by this command. ( Figure. 9 No operation ) Initialization The synchronous DRAM is initialized in the power-on sequence according to the following: 1. To stabilize internal circuits, when power is applied, a 100us or longer pause must precede any signal toggling. 2. After the pause, both banks must be precharged using the precharged command ( The precharge all banks command is convenient ). 3. Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. 4. Two or more Arto refresh must be performed. Remanks: 1. The sequence of Mode register programming and Refresh above may be transposed. 2. CKE and DQM must be held high until the precharge command is issued to ensure data-bus Hi-Z. Rev.01 10/33 64Mb SDRAM Programming the Mode Register The mode register is programmed by the Mode register set command using address bits BA through A0 as data inputs. The register retains data until it is reprogrammed or the device loses power. Options BA through A7 /CAS Latency A6 through A4 Wrap type A3 Burst Length A2 through A0 Following mode register programming, no command can be issued before at least 2 CLK elapsed. /CAS Latency /CAS Latency is the most critical of the parameters begin set. It tells the device how many clocks must elapse before the data will be available. Burst Length Burst length is the number of the words that will be output or input in a write cycle. After a read burst is completed, the output bus will become Hi-Z.