TFT-LCD Power Supply

® EL7586, EL7586A Data Sheet January 17, 2006 FN9210.2 TFT-LCD Power Supply The EL7586 and EL7586A represent multiple output regulators for use in all large panel, TFT-LCD applications. Both feature a single boost converter with an integrated 2A FET, two positive LDOs for VON and VLOGIC generation, and a single negative LDO for VOFF generation. The boost converter can be programmed to operate in either P-mode or PI-mode for improved load regulation. Both EL7586 and EL7586A also integrate fault protection for all four channels. Once a fault is detected, the device is latched off until the input supply or EN is cycled. EL7586 also features an integrated start-up sequence for VBOOST/VLOGIC, VOFF, then VON or for VLOGIC, VOFF, VBOOST, and VON. The latter requires a single external transistor. The timing of the start-up sequence is set using an external capacitor. EL7586A features an immediately-enabled VLOGIC output which is independent of EN input. The VLOGIC output will be switched off if a fault is detected and the power supply needs to be recycled to reset this condition. Both the EL7586 and EL7586A are pin-compatible, come in the 20 Ld 4x4 QFN package, and are specified for operation over the -40°C to +85°C temperature range. Features • 2A current limit FET options • 3V to 5V input • Up to 20V boost out • 1% regulation on all outputs • VLOGIC-VOFF-VBOOST-VON or VBOOST/VLOGIC-VOFF-VON sequence control - VLOGIC is on from start-up for EL7586A • Programmable sequence delay • Fully fault protected • Thermal shutdown • Internal soft-start • 20 Ld 4x4 QFN packages • Pb-free plus anneal available (RoHS compliant) Applications • LCD monitors (15”+) • LCD-TV (up to 40”+) • Notebook displays (up to 16”) • Industrial/medical LCD displays Ordering Information PART TAPE & PART NUMBER MARKING REEL EL7586ILZ (Note) EL7586ILZ-T7 (Note) EL7586ILZ-T13 (Note) EL7586AILZ (Note) EL7586AILZ-T7 (Note) 7586ILZ 7586ILZ 7586ILZ 7586AIL Z 7586AIL Z 7” 13” 7” 13” PACKAGE PKG. DWG. # Pinout EL7586, EL7586A (20 LD 4X4 QFN) TOP VIEW 17 SGND 19 VDD 16 FBB 15 CINT 14 VREF THERMAL PAD 13 PGND 12 PGND 11 FBN SGND 9 DRVN 10 FBP 6 DRVL 7 FBL 8 20 PG 18 EN 20 Ld 4x4 QFN MDP0046 (Pb-free) 20 Ld 4x4 QFN MDP0046 (Pb-free) 20 Ld 4x4 QFN MDP0046 (Pb-free) 20 Ld 4x4 QFN MDP0046 (Pb-free) 20 Ld 4x4 QFN MDP0046 (Pb-free) 20 Ld 4x4 QFN MDP0046 (Pb-free) CDLY 1 DELB 2 LX1 3 LX2 4 DRVP 5 EL7586AILZ-T13 7586AIL Z (Note) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL7586, EL7586A Absolute Maximum Ratings (TA = 25°C) VDELB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V VDRVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V VDRVN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V VLX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V VDRVL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Continuous Junction Temperature . . . . . . . . . . . . 125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER SUPPLY VS IS Supply Voltage VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from -40°C to 85°C, unless otherwise specified. CONDITION MIN TYP MAX UNIT DESCRIPTION 3 Enabled, LX not switching Disabled Enabled, LX not switching Disabled 1.7 750 1.7 10 5.5 2.5 900 2.5 20 V mA µA mA µA Quiescent Current (EL7586A) Quiescent Current (EL7586) IS CLOCK FOSC BOOST VBOOST VFBB Boost Output Range Boost Feedback Voltage TA = 25°C 5.5 1.192 1.188 VF_FBB VREF FBB Fault Trip Point Reference Voltage TA = 25°C 1.19 1.187 CREF DMAX ILXMAX ILEAK rDS(ON Eff I(VFBB) ∆VBOOST/ ∆VIN ∆VBOOST/ ∆IBOOST ∆VBOOST/ ∆IBOOST VCINT_T VREF Capacitor Maximum Duty Cycle Current Switch Switch Leakage Current Switch On-Resistance Boost Efficiency Feedback Input Bias Current Line Regulation Load Regulation - “P” Mode Load Regulation - “PI” Mode CINT Pl Mode Select Threshold See curves Pl mode, VFBB = 1.35V CINT = 4.7nF, IOUT = 100mA, VIN = 3V to 5.5V CINT pin strapped to VDD, 50mA < ILOAD < 250mA CINT = 4.7nF, 50mA < IO < 250mA 85 VLX = 16V 320 92 50 0.05 3 0.1 4.7 4.8 500 22 85 2.0 10 1.205 1.205 0.9 1.215 1.215 100 1.235 1.238 20 1.218 1.222 V V V V V V nF % A µA mΩ % nA %/V % % V Oscillator Frequency 900 1000 1100 kHz 2 FN9210.2 January 17, 2006 EL7586, EL7586A Electrical Specifications PARAMETER VON LDO VFBP FBP Regulation Voltage IDRVP = 0.2mA, TA = 25°C IDRVP = 0.2mA VF_FBP IFBP GMP ∆VON/∆I(VON) IDRVP IL_DRVP VOFF LDO VFBN FBN Regulation Voltage IDRVN = 0.2mA, TA = 25°C IDRVN = 0.2mA VF_FBN IFBN GMN ∆VOFF/ ∆I(VOFF) IDRVN IL_DRVN VLOGIC LDO VFBL FBL Regulation Voltage IDRVL = 1mA, TA = 25°C IDRVL = 1mA VF_FBL IFBL GML ∆VLOGIC/ ∆I(VLOGIC) IDRVL IL_DRL SEQUENCING tON tSS tDEL1 tDEL2 IDELB Turn On Delay Soft-start Time Delay Between AVDD and VOFF Delay Between VON and VOFF DELB Pull-down Current CDLY = 0.22µF CDLY = 0.22µF CDLY = 0.22µF CDLY = 0.22µF VDELB > 0.6V VDELB < 0.6V CDEL Delay Capacitor 10 30 2 10 17 50 1.4 220 ms ms ms ms µA mA nF FBL Fault Trip Point FBL Input Bias Current FBL Effective Transconductance VLOGIC Load Regulation DRVL Sink Current Max IL_DRVL VFBL falling VFBL = 1.35V VDRVL = 2.5V, IDRVL = 1mA to 8mA I(VLOGIC) = 100mA to 500mA VFBL = 1.1V, VDRVL = 2.5V VFBL = 1.5V, VDRVL = 5.5V 8 1.176 1.174 0.82 -500 200 0.5 16 0.1 5 1.2 1.2 0.87 1.224 1.226 0.92 500 V V V nA ms % mA µA FNN Fault Trip Point FBN Input Bias Current FBN Effective Transconductance VOFF Load Regulation DRVN Source Current Max DRVN Leakage Current VFBN falling VFBN = 0.2V VDRVN = -6V, IDRVN = 0.2mA to 2mA I(VOFF) = 0mA to 20mA VFBN = 0.3V, VDRVN = -6V VFBN = 0V, VDRVN = -20V 2 0.173 0.171 0.38 -250 50 -0.5 4 0.1 5 0.203 0.203 0.43 0.233 0.235 0.48 250 V V V nA ms % mA µA FBP Fault Trip Point FBP Input Bias Current FBP Effective Transconductance VON Load Regulation DRVP Sink Current Max DRVP Leakage Current VFBP falling VFBP = 1.35V VDRVP = 25V, IDRVP = 0.2 to 2mA I(VON) = 0mA to 20mA VFBP = 1.1V, VDRVP = 25V VFBP = 1.5V, VDRVP = 35V 2 1.176 1.172 0.82 -250 50 -0.5 4 0.1 5 1.2 1.2 0.87 1.224 1.228 0.92 250 V V V nA ms % mA µA VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from -40°C to 85°C, unless otherwise specified. (Continued) CONDITION MIN TYP MAX UNIT DESCRIPTION 3 FN9210.2 January 17, 2006 EL7586, EL7586A Electrical Specifications PARAMETER FAULT DETECTION tFAULT OT IPG Fault Time Out Over-temperature Threshold PG Pull-down Current VPG > 0.6V VPG < 0.6V LOGIC ENABLE VHI VLO ILOW IHIGH Logic High Threshold Logic Low Threshold Logic Low Bias Current Logic High Bias Current at VEN = 5V 12 0.2 18 2.3 0.8 2 24 V V µA µA CDLY = 0.22µF 50 140 15 1.7 ms °C µA mA VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from -40°C to 85°C, unless otherwise specified. (Continued) CONDITION MIN TYP MAX UNIT DESCRIPTION Pin Descriptions PIN NAME 1 2 3, 4 5 6 7 8 9, 17 10 11 12, 13 14 15 16 18 19 20 PIN NUMBER CDLY DELB LX1, LX2 DRVP FBP DRVL FBL SGND DRVN FBN PGND VREF CINT FBB EN VDD PG DESCRIPTION A capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault timeout time Open drain output for gate drive of optional VBOOST delay FET Drain of the internal N channel boost FET; for EL7586, pin 4 is not connected Positive LDO base drive; open drain of an internal N channel FET Positive LDO voltage feedback input pin; regulates to 1.2V nominal Logic LDO base drive; open drain of an internal N channel FET Logic LDO voltage feedback input pin; regulates to 1.2V nominal Low noise signal ground Negative LDO base drive; open drain of an internal P channel FET Negative LDO voltage feedback input pin; regulates to 0.2V nominal Power ground, connected to source of internal N channel boost FET Bandgap voltage bypass, connect a 0.1µF to SGND VBOOST integrator output, connect capacitor to SGND for PI mode or connect to VDD for P mode operation Boost regulator voltage feedback input pin; regulates to 1.2V nominal Enable pin, High = Enable; Low or floating = Disable Positive supply Push-pull gate drive of optional fault protection FET, when chip is disa