TP-UART-IC

TECHNICAL DATA EIB-TP-UART-IC Features VB Tx0 Rx IN MODE 0 MODE 1 TEST MODE X1 X2 TSTOUT RxD 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 VB + VSP CSA VCC DIV • Signaling for standard UART (LSB-First, Idle is 1) • Baud rate 9600 or 19200 baud for the communication: TP - UART <--> Host - Controller • Direct coupling to host controller (TxD, RxD), or via optical couplers (optional) SAVE TSTIN • 2 - wire protocol with software handshake VIF RESn TxD • Buffering of send frames • No critical timing during transmission • 64 Byte telegram buffer • Operating temperature range: -25°C to 85°C • Supervision of EIB bus voltage GENERAL DESCRIPTION The TP - UART - IC (Twisted Pair - Universal Asynchronous Receive Transmit - IC) is a transceiver which supports the connection of microcontrollers of sensors, actuators, or other applications to the EIB (European - Installation - Bus). This module supports every transmit- and receive - function and also the high ohmic decoupling of energy from bus line. It generates further a stabilized 3.3V or 5V supply to use by a host controller. Up to 256 subscribers can be connected to one bus line. An UART interface is realized for communication with a host controller. The coupling can be realized directly or via optical couplers. The TP - UART - IC consists of two main parts: the digital part (UART - Interface) and the analog part ( analog circuit part). The reproduction, transmission or use of this document or it‘ contents is not permitted without express written authority. All s rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 1 TP-UART-IC GENERAL DRAWING + Power Supply A - Bus 230V / 50Hz 30V - B - Bus Optional Electrical Isolation (Optocoupler) TP-UARTIC RxD TxD RxD TP-UARTIC TxD RxD TP-UARTIC TxD Application Application ... Application Optional Power Supply Bus Device 1 Bus Device 2 Bus Device n STRUCTURE of TP - UART - IC (Block Diagram:) Host-Controller RxD UART-Receiver 64 Byte TelegramSendbuffer TxD UART-Transmitter RESn TSTIN_BDS (Baud rate) TSTout Mode 0 Mode 1 EIB-Receiver EIB-Transmitter EIB-Transmit RxD3 Filter EIB-ReceiveTxD3 4,9152 MHz 0,05 % Digital - Part Controll-Logic State-Byte ACK-Flags 1 Bytebuffer (receive) Analog - Part Transmit Power Supply 5 V Regulator Receive EIB The reproduction, transmission or use of this document or it‘ contents is not permitted without express written authority. All s rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 2 TP-UART-IC 1 1.1 The ANALOG - PART General Device Specification 1.1.1 Absolute Maximum Ratings All voltages are referring to VB-. Currents are declared positive in case of flowing into pin. Symbol VB+ VCC VIF VVSP VTxO VRxIN VLV1 VLV2 ϑj ϑS VESD Parameter positive line voltage positive voltage supply (internal or external supply) positive external voltage supply interstate voltage (generated by on-chip regulator) voltage on pin Tx0 voltage on pin RxIN voltage on low voltage pins MODE0, MODE1, TSTIN, TESTMODE voltage on low voltage pins TxD, RESn, TSTOUT, X1, X2, RxD junction temperature storage temperature Min -0.5 -0.5 -0.5 -0.5 -0.5 -15 -0.5 -0.5 Max Unit Note 45 V 1) 7 V 2) 7 V 2) 13 V 2) 45 V 1) 45 V 1) 4) VCC +0.5 V VIF +0.5 170 -65 170 ± 1000 V ο ο C C V 3) mA 71.5 K/W 1 W -20 V for 2 µsec and 65 V for 150 µsec 2) Allowed voltage relations: (a) VCC and VVSP normal / VB+ and VIF can be 0 V (b) VVSP normal / VCC , VB+ and VIF can be 0 V (c) VIF normal / VCC , VB+ and VVSP can be 0 V The combination: VCC normal and VVSP = 0 V is not allowed! 3) Human body model: 100 pF, 1.5 kΩ 4) Dynamic via CREC= 47 nF in case of switching-on the bus voltage max. ESD stress voltage ILATCHUP static current for latchup initialization ± 50 Rth thermal resistance of the SOIC-20 package 58.5 PV maximum power dissipation 1) During surge impulse is allowed and guaranteed by ext. elements: 1.1.2 Recommended Operating Conditions Symbol VB+ VCC Parameter positive line voltage positive voltage supply for external supply (digital test modes with SHB = 0) positive external supply voltage ambient temperature Min 20 4.75 Max 33 5.25 Unit Note V 1) V V C MHz ο VIF 3.0 5.25 -25 85 ϑamb fclk clock frequency (external quartz) 4.9152 1) DC voltage of bus, with signal and compensation pulse 11 V ... 45 V 1.1.3 Humidity Level The valid susceptibility against humidity is described by JEDEC JESD22-A112, table 1, level 5. The reproduction, transmission or use of this document or it‘ contents is not permitted without express written authority. All s rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 3 TP-UART-IC 1.2 DC and AC Characteristics The following parameters are valid in the ambient temperature range ϑamb = -25 οC to 85 οC and for bus voltage VB+ = 20 to 33 V if it is not otherwise declared. When the bus voltage is lower than 20 V and no RESET is active then the normal functionality must be fulfilled, but the parameters may be outside the limits. 1.2.1 Bus Pins VB+ and VB- (Pins 10, 11) Via these pins the ASIC is connected to the bus line. VB- represents the reference potential. Symbol Parameter Min Max Unit Note VVB+ positive line voltage -0.5 45 V 1) Inormal current consumption in analog mode (without clock) 1 mA Inormal current consumption in normal mode (with clock) 1.6 mA 4,9152 MHz 1) during surge impulse is allowed and guaranteed by ext. Elements: -20 V for 2 µs and 65 V for 150 µs 1.2.2 Buffer Voltage VSP (Pin 9) The ASIC delivers a supply voltage of 5 volts to external loads. In order to prevent a rapid change of bus current as a result of a rapid change of the load an external capacitor at the pin VSP is used for energy storage. The static voltage is adjusted to app. 8,8 V (8,2 ...9,2) by an internal regulator. Symbol Parameter Min Max Unit VVSP Energy buffer voltage 5.76 13 V CVSP External storage capacitor 80 µF 1) due to the limited current changing rate an overshoot of VVSP after load change may occur 2) recommended 100 µF; must be larger than the capacitor at VCC Note 1) 2) 1.2.3 Current Controlling Pin CSA (Pin 8) An external capacitor at this pin prevents a quick change of ASIC current in case of quick changing bus voltage VB+ or load current IVCC. The ASIC current changes with a rate of max. 0,5 mA/ms (CCSA = 47 nF). Symbol Parameter CCR max. current changing rate (ext. Start, CCSA = 47 nF) 1)tolerance of capacitor CCSA = 47nF/50V +/- 5% Min 0.2 Max 0.5 Unit mA/ms Note 1) The reproduction, transmission or use of this document or it‘ contents is not permitted without express written authority. All s rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 4 TP-UART-IC 1.2.4 Supply Pin VCC (Pin 7) The pin VCC delivers the internal generated voltage supply to external loads. An external short-circuit from the VCC pin to GND will not cause a destruction of the ASIC. Parameter Min Max Unit Note Voltage supply (generated by the ASIC or external 4.75 5.25 V 1) source in case of digital test modes) CVCC External storage capacitor 6,8 10 µF +/-20 % IVCC External load at VCC 10 mA 2) 1) VB+ ≥ 11 V 2) If there is a current leap ILeap with a slope greater than 1 mA/ms the following formulas have to be applied: IStat is the static current, i.e. slope not greater than 1 mA/ms IStat ≤ 3 mA; ILeap ≤ (3 mA – IStat) + 5 mA 3mA < IStat ≤ 5 mA; ILeap ≤ 8 mA - IStat IStat > 5 mA; ILeap ≤ 3 mA Symbol VVCC 1.2.5 Receive Pin RxIN (Pin 13) The Receive Pin RxIN is coupled to the EIB bus by an external capacitor. Symbol Parameter CREC external coupling capacitor 1) external capacitor 47 nF/50V ± 5% Min 44.5 Max 49.5 Unit Note 1) nF typ.47 nF 1.2.6 Transmit Pin TxO (Pin 12) The transmit pin is connected to EIB via external resistor of typ. 68Ω /1W (see Typical Application Circuits). Symbol Parameter VTRANS transmit voltage 1) related to VB+ Min -6 Max -9 Unit Note V 1) 1.2.7 Supply Pin VIF (Pin 3) The Pin VIF is used as supply voltage for the pins TxD, RxD, RESn, TSTOUT, X1, X2 and determines their high input or output level. Symbol VIF CVIF Parameter external supply voltage for interface external storage capacitor Min 3 10 Max 5.5 Unit V nF Note 1) 2) 1) Typical supply voltages: 3.3 V or 5 V 2) Recommended The reproduction, transmission or use of this document or it‘ contents is not permitted without express written authority. All s rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 5 TP-UART-IC 1.2.8 Oscillator Pins X1 and X2 (Pins 17, 18) The oscillator pins X1 and X2 are used to connect directly a quartz of 4.9152 MHz without additional external capacitors. These pins are ESD protected to VB - and VIF. Symbol Parameter Min Max Unit Note VX1/2 Oscillator voltage at X1 and X2 -0.5 VIF + 0.5 V VIL Voltage range for input low level 0 0.25 * VIF VIH Voltage range for input high level 0.75 * VIF 1.0 * VIF fclk Clock frequency 2,4576 4,9152 MHz 1) 1) 4,9152 MHz (DIV = VCC) or 2.4576 MHz (DIV = VB -); Tolerance: ±0,05 %; no other clock frequencies Operation Mode Normal Mode with external Clock Analog Mode X1 Clock VBX2 open open 1.2.9 Internal Clock Divider Pin DIV (Pin 6) This input pin activates an internal 2:1 clock divider. If a 4.9152 MHz clock is used (quartz or external clock) then pin DIV must be connected to VCC. If an 2.4576 MHz clock is used (only external clock) then this pin must be connected to VB -. Symbol VIL VIH Parameter voltage range for input low level voltage range f