ECP2/M Family

www.DataSheet4U.com LatticeECP2/M Family Data Sheet DS1006 Version 02.2, December 2006 www.DataSheet4U.com LatticeECP2/M Family Data Sheet Introduction December 2006 Advance Data Sheet DS1006 Features ■ High Logic Density for System Integration • 6K to 95K LUTs • 90 to 616 I/Os ■ Pre-Engineered Source Synchronous I/O • DDR registers in I/O cells • Dedicated gearing logic • Source synchronous standards support – SPI4.2, SFI4 (DDR Mode), XGMII – High Speed ADC/DAC devices • Dedicated DDR and DDR2 memory support – DDR1/DDR2 400 (200MHz) • Dedicated DQS support ■ Embedded SERDES (LatticeECP2M Only) • Data Rates 540 Mbps to 3.125 Gbps • 270 Mbps with Half Rate mode Up to 16 channels per device PCI Express, Ethernet (1GbE, SGMII), OBSAI, CPRI and Serial RapidIO. ■ sysDSP™ Block • 3 to 42 blocks for high performance multiply and accumulate • Each block supports – One 36x36, four 18X18 or eight 9X9 multipliers ■ Programmable sysIO™ Buffer Supports Wide Range Of Interfaces • • • • • • • • • • • LVTTL and LVCMOS 33/25/18/15/12 SSTL 3/2/18 I, II HSTL15 I and HSTL18 I, II PCI and Differential HSTL, SSTL LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL 1149.1 Boundary Scan compliant Dedicated bank for configuration I/Os SPI boot flash interface Dual boot images supported TransFR™ I/O for simple field updates Soft Error Detect macro embedded ■ Flexible Memory Resources • 55Kbits to 5308Kbits sysMEM™ Embedded Block RAM (EBR) – 18Kbit block – Single, pseudo dual and true dual port – Byte Enable Mode support • 12K to 202Kbits distributed RAM – Single port and pseudo dual port ■ Flexible Device Configuration ■ sysCLOCK Analog PLLs and DLLs • Two GPLLs and up to six SPLLs per device – Clock multiply, divide, phase & delay adjust – Dynamic PLL adjustment • Two general purpose DLLs per device ■ Optional Bitstream Encryption ■ System Level Support • ispTRACY™ internal logic analyzer capability • Onboard oscillator for initialization & general use • 1.2V power supply Table 1-1. LatticeECP2 Family Selection Guide Device LUTs (K) Distributed RAM (Kbits) EBR SRAM (Kbits) EBR SRAM Blocks sysDSP Blocks 18x18 Multipliers GPLL + SPLL + DLL Maximum Available I/O Packages and I/O Combinations 144-pin TQFP (20 x 20 mm) 208-pin PQFP (28 x 28 mm) 256-ball fpBGA (17 x 17 mm) 484-ball fpBGA (23 x 23 mm) 190 90 93 131 193 297 131 193 331 331 339 ECP2-6 6 12 55 3 3 12 2+0+2 190 ECP2-12 12 24 221 12 6 24 2+0+2 297 ECP2-20 21 42 276 15 7 28 2+0+2 402 ECP2-35 32 64 332 18 8 32 2+0+2 450 ECP2-50 48 96 387 21 18 72 2+2+2 500 ECP2-70 68 136 1032 56 22 88 2+4+2 583 © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1006 Introduction_01.1 www.DataSheet4U.com Lattice Semiconductor Table 1-1. LatticeECP2 Family Selection Guide (Continued) Device 672-ball fpBGA (27 x 27 mm) 900-ball fpBGA (31 x 31 mm) ECP2-6 ECP2-12 ECP2-20 402 Introduction LatticeECP2/M Family Data Sheet ECP2-35 450 ECP2-50 500 ECP2-70 500 583 Table 1-2. LatticeECP2M Family Selection Guide Device LUTs (K) sysMEM Blocks (18kb) Embedded Memory (Kbits) Distributed Memory (Kbits) sysDSP Blocks 18x18 Multipliers GPLL+SPLL+DLL Maximum Available I/O 256-ball fpBGA (17 x 17 mm) 484-ball fpBGA (23 x 23 mm) 672-ball fpBGA (27 x 27 mm) 900-ball fpBGA (31 x 31 mm) 1156-ball fpBGA (35 x 35 mm) ECP2M20 19 66 1217 41 6 24 2+6+2 304 4 / 140 4 / 304 ECP2M35 34 114 2101 71 8 32 2+6+2 410 4 / 140 4 / 303 4 / 410 4 / 270 8 / 381 8 / 438 16 / 452 16 / 452 16 / 616 ECP2M50 48 225 4147 101 22 88 2+6+2 438 ECP2M70 67 246 4534 145 24 96 2+6+2 452 ECP2M100 95 288 5308 202 42 168 2+6+2 616 Packages and SERDES / I/O Combinations Introduction The LatticeECP2/M family of FPGA devices has been optimized to deliver high performance features such as advanced DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an economical FPGA fabric. This combination was achieved through advances in device architecture and the use of 90nm technology. The LatticeECP2/M FPGA fabric was optimized for the new technology from the outset with high performance and low cost in mind. The LatticeECP2/M devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP blocks and advanced configuration support, including encryption and dual boot capabilities. The LatticeECP2M family of devices features high speed SERDES with PCS. These high jitter tolerance and low transmission jitter SERDES with PCS blocks can be configured to support an array of popular data protocols including PCI Express, Ethernet (1GbE and SGMII), OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization settings make SERDES suitable for chip to chip and small form factor backplane applications. The ispLEVER® design tool from Lattice allows large complex designs to be efficiently implemented using the LatticeECP2/M family of FPGA devices. Synthesis library support for LatticeECP2/M is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP2/M device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP2/M family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 1-2 www.DataSheet4U.com LatticeECP2/M Family Data Sheet Architecture December 2006 Advance Data Sheet DS1006 Architecture Overview Each LatticeECP2/M device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sysDSP™ Digital Signal Processing blocks as shown in the ECP2-6 in Figure 2-1. In addition, the LatticeECP2M family contain SERDES Quads in one or more of the corners. Figure 2-2 shows the block diagram of ECP2M20 with one quad. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a twodimensional array. Only one type of block is used per row. The LatticeECP2/M devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated 18K fast memory blocks. Each sysMEM block can be configured in variety of depths and widths of RAM or ROM. In addition, LatticeECP2/M devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and adder/ accumulators, which are the building blocks for complex signal processing capabilities. The LatticeECP2M devices feature up to 16 embedded 3.125Gbps SERDES (Serializer / Deserializer). Each SERDES Channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each group of four SERDES along with its Physical Coding Sub-layer (PCS) block creates a Quad. The functionality of the SERDES/PCS Quads can be controlled by memory cells set during device configuration or by registers addressable during device operation. The registers in every quad can be programmed by a soft IP interface, referred to as the SERDES Client Interface (SCI). These quads (up to four) are located at the corners of the devices. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO buffers. The sysIO buffers of the LatticeECP2/M devices are arranged into eight banks, allowing the implementation of a wide variety of I/O standards. In addition, a separate I/O bank is provided for the programming interfaces. PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support to aid in the implementation of the high speed source synchronous standards such as SPI4.2 along with memory interfaces including DDR2. Other blocks provided include PLLs, DLLs and configuration functions. The LatticeECP2/M architecture provides two General PLLs (GPLL) and up to six Standard PLLs (SPLL) per device. In addition, each LatticeECP2/M family member provides two DLLs per device. The GPLLs and DLLs blocks are located in pairs at the end of the bottommost EBR row; the DLL block located towards the edge of the device. The SPLL blocks are located at the end of the other EBR/DSP rows. The configuration block that supports features such as configuration bit-stream decryption, transparent updates and dual boot support is located toward the center of this EBR row. Every device in the LatticeECP2/M family supports a sysCONFIG™ port located in the corner between banks four and five, which allows for serial or parallel device configuration. In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error detect capability. The LatticeECP2/M devices use 1.2V as their core voltage. © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered t