Test Bus Controller

www.DataSheet4U.com EB203 Test Bus Controller SN74ACT8990 Author Peter Forstner Date: 01.07.92 Rev.: 1.0 TEXAS INSTRUMENTS This report describes the IEEE 1149.1 Test Bus Controller SN74ACT8990 from Texas Instruments. The first part explains the architecture and operation of the Test Bus Controller; the second part uses examples to explain the programming procedure. www.DataSheet4U.com 2 EB203 TEXAS INSTRUMENTS Contents: Contents: 1. Introduction................................................................................................ 5 2. Hardware .................................................................................................... 8 2.1. The Processor Interface................................................................... 8 2.2. The Test Bus Interface................................................................... 10 2.3. Architecture.................................................................................... 13 2.3.1. SEQUENCE BLOCK........................................................... 13 2.3.2. SERIAL BLOCK.................................................................. 15 2.3.3. EVENT BLOCK................................................................... 17 2.3.4. COUNTER BLOCK............................................................. 21 2.3.5. COMMAND BLOCK............................................................ 22 2.3.6. HOST BLOCK..................................................................... 23 3. Programming ........................................................................................... 24 3.1. The Registers................................................................................. 25 CONTROL0 .................................................................................. 26 CONTROL1 .................................................................................. 27 CONTROL2 .................................................................................. 28 CONTROL3 .................................................................................. 29 CONTROL4 .................................................................................. 30 CONTROL5 .................................................................................. 31 CONTROL6 .................................................................................. 32 CONTROL7 .................................................................................. 34 CONTROL8 .................................................................................. 36 CONTROL9 .................................................................................. 37 MINOR COMMAND ...................................................................... 38 MAJOR COMMAND ..................................................................... 41 COUNTER1 UPDATE0................................................................. 44 COUNTER1 UPDATE1................................................................. 44 COUNTER2 UPDATE0................................................................. 44 COUNTER2 UPDATE1................................................................. 44 STATUS0...................................................................................... 45 STATUS1...................................................................................... 46 STATUS2...................................................................................... 47 STATUS3...................................................................................... 47 CAPTURE0................................................................................... 48 CAPTURE1................................................................................... 48 READ BUFFER ............................................................................ 48 WRITE BUFFER........................................................................... 48 3.2. Typical Programming Procedure.................................................... 49 www.DataSheet4U.com EB203 3 Contents: TEXAS INSTRUMENTS 4. Examples.................................................................................................. 52 4.1. Example Test Board....................................................................... 52 4.2. Software Examples ........................................................................ 53 4.2.1. Load commands in test board ............................................ 54 4.2.2. Load test vector in test board ............................................. 59 4.2.3. Copy SHIFTER-FIFO into the READ BUFFER................... 63 4.2.4. EXTEST.............................................................................. 64 4.2.5. PRPG/PSA ......................................................................... 69 4.2.6. Event controlled PRPG/PSA............................................... 78 5. Summary .................................................................................................. 82 www.DataSheet4U.com 4 EB203 TEXAS INSTRUMENTS Introduction 1. Introduction There has been a dramatic increase in the complexity of electronic systems, as a result of advances in the integration of semiconductors, the introduction of new packaging techniques (SMD), and the consequent use of doublesided circuit boards. However, increased component density on circuit boards brings with it new problems of testability, since the number of the necessary test vectors increases out of proportion with complexity. By making use of nail bed adapters, it is possible to partition the system to be tested, and so to reduce significantly the number of test vectors, although high SMD component density on double-sided boards reduces the number of possible contact areas for nail bed adapters. The escalating problems of testability can therefore only be solved with a completely new concept. Back in 1985, leading electronic manufacturers founded the Joint Test Action Group (JTAG), in order to develop a new and cost-effective test concept. The result of this was the IEEE 1149.1 standard. This standard requires the use of special test-circuits at the inputs and outputs of selected semiconductor components, together with logic to control such test-circuits. A 4-wire serial test bus combines the test-circuits into a complete test-group, which is controlled via the test bus; in this way, with only 4 lines the complete system can be partitioned and tested. The Texas Instruments(TI) Application Report EB193 describes these test methods in detail, and presents the IEEE 1149.1-compatible SCOPE™ bus drivers from TI. This Application Report EB203 assumes an understanding of test-methods according to IEEE 1149.1 The control of an IEEE 1149.1-compatible test system is usually performed by a computer. The TEST BUS CONTROLLER (TBC) SN74ACT8990 from Texas Instruments can be connected to a computer like a normal interface circuit, and it then controls completely the IEEE 1149.1 test bus.(Figure 1). The computer first configures the TBC, and then loads in parallel the test commands and test vectors. The TBC transfers these commands and vectors to the system, and thereby generates the signal sequence required by IEEE 1149.1. The processor can read the result in parallel from the TBC, after the test data has addressed the logic to be tested. This Application Report describes the operation of the TBC, and explains the programming procedure with examples. www.DataSheet4U.com EB203 5 Introduction TEXAS INSTRUMENTS Figure 1: Test System with the SN74ACT8990 TEST BUS CONTROLLER In order to reduce the applications work needed from the user to control IEEE 1149.1-compatible test systems, TI offers the computer program ASSET (ADVANCED SUPPORT SYSTEM FOR EMULATION AND TEST) together with a plug-in computer board. The TEST BUS CONTROLLER SN74ACT8990 is used on this board. ASSET allows an easy development of test programs; for this, the user needs no understanding of the function of the TEST BUS CONTROLLER. First, a library with the IEEE 1149.1compatible circuits which are to be used must be assembled; a library with all standard TI components is supplied. Then, the complete system to be tested must be described with components from the library. After the system description, ASSET needs only the test vectors before testing can begin. This system is also ideally suited to supporting the circuit designer during the test phase. www.DataSheet4U.com Figure 2: System with BIST (BUILT IN SELF TEST) If BIST (BUILT IN SELF TEST) is to be incorporated into an electronic system, the TEST BUS CONTROLLER SN74ACT8990 in combination with the SCAN PATH SELECTOR SN74ACT8999 and a microprocessor provide 6 EB203 TEXAS INSTRUMENTS Introduction an ideal basis (Figure 2). The main computer can give the microprocessor the signal to start BIST via the IEEE 1149.1 test bus. The result of the self test is now communicated from the microprocessor to the main computer. If a large system is composed of several subsystems, it is advantageous to have BIST in each subsystem. The self-test can then be implemented simultaneously in all subsystems, resulting in an enormous reduction of test time. This is one of the cases in which direct programming of the TEST BUS CONTROLLER is necessary, and in which this Application Report is intended to give assistance. www.DataSheet4U.com EB203 7 Hardware TEXAS INSTRUMENTS 2. Hardware The TEST BUS CONTROLLER SN74ACT8990 provides the interface between a processor and the IEEE 1149.1 test bus. Both interfaces can be operated asynchronously, that is, the clock of the computer does not need to be synchronized with the test clock TCK. 2.1. The Processor Interface The processor interface consists of the following: ⇒ ⇒ ⇒ ⇒ ⇒ www.DataSheet4U.com 5 Bit Address Bus A0 .. A4, 16 Bit Data Bus D0 .. D15, A Read Line /RD, A Write Line /WR, A Status Line /RDY, and An Interrupt Line /INT ⇒ The TBC is connected to t