Description
E n n n n n n n 28F016SA 16-MBIT (1 MBIT X 16, 2 MBIT X 8) FlashFile™ MEMORY Includes Commercial and Extended Temperature Specifications User-Selectable 3.3V or 5V V CC User-Configurable x8 or x16 Operation 70 ns Maximum Access Time 28.6 MB/sec Burst Write Transfer Rate 1 Million Typical Erase Cycles per Block 56-Lead, 1.2 mm x 14 mm x 20 mm TSOP Package 56-Lead, 1.8 mm x 16 mm x 23.7 mm SSOP Package n Revolutionary Architecture  Pipelined Command Execution  Program during Erase  Command Superset of Intel 28F008SA 1 mA Typical I CC in Static Mode 1 µA Typical Deep Power-Down 32 Independently Lockable Blocks State-of-the-Art 0.6 µm ETOX™ IV Flash Technology n n n n Intel’s 28F016SA 16-Mbit FlashFile™ memory is a revolutionary architecture which is the ideal choice for designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative capabilities, low-power, extended temperature operation and high read/program performance, the 28F016SA enables the design of truly mobile, high-performance communications and computing products. The 28F016SA is the highest density, highest performance nonvolatile read/program solution for solid-state storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit FlashFile memory), extended cycling, extended temperature operation, flexible VCC, fast program and read performance and selective block locking provide highly flexible memory components suitable for Resident Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives. The 28F016SA dual read voltage enables the design of memory cards which can be interchangeably read/written in 3.3V and 5.0V systems. Its x8/x16 architecture allows optimization of the memory-to-processor interface. Its high read performance and flexible block locking enable both storage and execution of operating systems and application software. Manufactured on Intel’s 0.6 µm ETOX IV process technology, the 28F016SA is the most cost-effective, highest density monolithic 3.3V FlashFile memory. November 1996 Order Number: 290489-004 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F016SA may contain design defects or errors known as errata. Current characterized errata are available upon request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 COPYRIGHT © INTEL CORPORATION, 1996 CG-041493 E 28F016SA CONTENTS PAGE PAGE 5.6 AC Characteristics–Read Only Operations.................................................32 5.7 Power-Up and Reset Timings.....................37 5.8 AC Characteristics for WE#–Controlled Command Write Operations ......................38 5.9 AC Characteristics for CE#–Controlled Command Write Operations ......................42 5.10 AC Characteristics for Page Buffer Write Operations.................................................46 5.11 Erase and Word/Byte Program Performance, Cycling Performance and Suspend Latency.......................................49 6.0 DERATING CURVES.....................................50 7.0 MECHANICAL SPECIFICATIONS FOR TSOP ............................................................52 8.0 MECHANICAL SPECIFICATIONS FOR SSOP............................................................53 APPENDIX A: Device Nomenclature and Ordering Information ..................................54 APPENDIX B: Additional Information ...............55 1.0 INTRODUCTION ............................................. 5 1.1 Product Overview ........................................ 5 2.0 DEVICE PINOUT............................................. 6 2.1 Lead Descriptions ........................................ 8 3.0 MEMORY MAPS ........................................... 12 3.1 Extended Status Register Memory Map..... 13 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS............. 14 4.1 Bus Operations for Word-Wide Mode (BYTE# = VIH)........................................... 14 4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL) ........................................... 14 4.3 28F008SA–Compatible Mode Command Bus Definitions.......................................... 15 4.4 28F016SA–Performance Enhancement Command Bus Definitions......................... 16 4.5 Compatible Status Register ....................... 18 4.6 Global Status Register ............................... 19 4.7 Block Status Register ................................ 20 5.0 ELECTRICAL SPECIFICATIONS ................. 21 5.1 Absolute Maximum Ratings ....................... 21 5.2 Capacitance............................................... 22 5.3 Timing Nomenclature................................. 23 5.4 DC Characteristics (VCC = 3.3V ± 10%) ..... 26 5.5 DC Characteristics (VCC = 5.0V ± 10%, 5.0V ± 5%) ................ 29 3 28F016SA E REVISION HISTORY Description Original Version — Added 56-Lead SSOP Package — Separated AC Reading Timing Specs tAVEL, tAVGL for Extended Status Register Reads — Modified Device Nomenclature — Added Ordering Information — Added Page Buffer Typical Program Performance numbers — Added Typical Erase Suspend Latencies — For ICCD (Deep Power-Down current) BYTE# must be at CMOS levels — Added SSOP package mechanical specifications — Revised document status from “Advanced Information” to “Preliminary” — Section 5.11: Renamed specification “Erase Suspend Latency Time to Program” as “Auto Erase Suspend Latency Time to Program” — Section 5.7: Added specifications t PHEL3, tPHEL5 — TSOP dimension A1 = 0.05 mm (min) — SSOP dimension B = 0.40 mm (max) — Minor cosmetic changes Update: —Changed Deep Power Down Current — Changed Standby Current — Changed Sleep Mode Current Combined Commercial and Extended Temperature information into single datasheet Number -001 -002 -003 -004 4 E 1.0 1.1 28F016SA Internal algorithm automation allows word/byte programs and block erase operations to be executed using a two-write command sequence to the CUI in the same way as the 28F008SA 8-Mbit FlashFile memory. A superset of commands have been added to the basic 28F008SA command-set to achieve higher program performance and provide additional capabilities. These new commands and features include: • • • • • • Page Buffer Writes to Flash Command Queueing Capability Automatic Data Programs during Erase Software Locking of Memory Blocks Two-Byte Systems Successive Programs in 8-bit INTRODUCTION The documentation of the Intel 28F016SA memory device includes this datasheet, a detailed user’s manual, and a number of application notes, all of which are referenced at the end of this datasheet. The datasheet is intended to give an overview of the chip feature-set and of the operating AC/DC specifications. The 16-Mbit Flash Product Family User’s Manual provides complete descriptions of the user modes, system interface examples and detailed descriptions of all principles of operation. It also contains the full list of software algorithm flowcharts, and a brief section on compatibility with Intel 28F008SA. Product Overview The 28F016SA is a high-performance 16-Mbit (16,777,216 bit) block erasable nonvolatile random access memory organized as either 1 Mword x 16 or 2 Mbyte x 8. The 28F016SA includes thirtytwo 64-KB (65,536) blocks or thirty-two 32-KW (32,768) blocks. A chip memory map is shown in Figure 4. The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease-of-use. Among the 28F016SA: • • • significant enhancements on the Erase All Unlocked Blocks Writing of memory data is performed in either byte or word increments typically within 6 µs, a 33% improvement over the 28F008SA. A block erase operation erases one of the 32 blocks in typically 0.6 sec, independent of the other blocks, which is a 65% improvement over the 28F008SA. Each block can be written and erased a minimum of 100,000 cycles. Systems can achieve typically onemillion block erase cycles by providing wear-leveling algorithms and graceful block retirement. These techniques have already been employed in many flash file systems. Additionally, wear leveling of block erase cycles can be used to minimize the program/erase performance differences across blocks. The 28F016SA incorporates two Page Buffers of 256 bytes (128 words) each to allow page data writes. This feature can improve a system write performance by up to 4.8 times over previous flash memory devices. All operations are started by a sequence of command writes to the device. Three Status Registers (described in detail later) and a RY/BY# output pin provide information on the progress of the requested operation. While the 28F008SA requires an operation to complete before the next operation can be requested, the 28F016SA allow

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