24-BIT DIGITAL SIGNAL PROCESSOR

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by: DSP56002/D, Rev. 3 DSP56002 24-BIT DIGITAL SIGNAL PROCESSOR The DSP56002 is a MPU-style general purpose Digital Signal Processor (DSP) composed of an efficient 24-bit DSP core, program and data memories, various peripherals, and support circuitry. The DSP56000 core is fed by on-chip Program RAM, and two independent data RAMs. The DSP56002 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI), parallel Host Interface (HI), Timer/Event Counter, Phase Lock Loop (PLL), and an On-Chip Emulation (OnCE™) port. This combination of features, illustrated in Figure 1, makes the DSP56002 a cost-effective, high-performance solution for high-precision general purpose digital signal processing. 1 6 3 15 16-bit Bus 24-bit Bus Program Memory 512 × 24 RAM 64 × 24 ROM (boot) X Data Memory 256 × 24 RAM 256 × 24 ROM (A-law/ µ-law) Y Data Memory 256 × 24 RAM 256 × 24 ROM (sine) 24-bit Timer/ Event Counter Sync. Serial (SSI) or I/O Serial Comm. (SCI) or I/O Host Interface (HI) or I/O 24-bit 56000 DSP Core Internal Data Bus Switch OnCE™ Port PLL Clock Gen. 7 4 Address Generation Unit PAB XAB YAB GDB PDB XDB YDB External Address Bus Switch Address 16 External Data Bus Switch Data 24 Interrupt Control Program Decode Controller Program Address Generator Data ALU 24 × 24 + 56 → 56-bit MAC Two 56-bit Accumulators Bus Control Control 10 Program Control Unit 3 IRQ AA0604 Figure 1 DSP56002 Block Diagram ©1996 MOTOROLA, INC. SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 FOR TECHNICAL ASSISTANCE: Telephone: Email: Internet: 1 (800) 521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com Data Sheet Conventions This data sheet uses the following conventions: OVERBAR “asserted” “deasserted” Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN Note: Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. ii DSP56002/D, Rev. 3 MOTOROLA DSP56002 Features FEATURES Digital Signal Processing Core • • • • • • • • • • • • • • Efficient 24-bit DSP56000 core Up to 40 Million Instructions Per Second (MIPS), 25 ns instruction cycle at 80 MHz; up to 33 MIPS, 30.3 ns instruction cycle at 66 MHz Up to 240 Million Operations Per Second (MOPS) at 80 MHz; up to 198 MOPS at 66 MHz Performs a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks Highly parallel instruction set with unique DSP addressing modes Two 56-bit accumulators including extension bits Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles 56-bit addition/subtraction in 1 instruction cycle Fractional and integer arithmetic with support for multiprecision arithmetic Hardware support for block-floating point FFT Hardware nested DO loops Zero-overhead fast interrupts (2 instruction cycles) Four 24-bit internal data buses and three 16-bit internal address buses for maximum information transfer on-chip Memory • • • • • • On-chip Harvard architecture permitting simultaneous accesses to program and two data memories 512 × 24-bit on-chip Program RAM and 64 × 24-bit bootstrap ROM Two 256 × 24-bit on-chip data RAMs Two 256 × 24-bit on-chip data ROMs containing sine, A-law, and µ-law tables External memory expansion with 16-bit address and 24-bit data buses Bootstrap loading from external data bus, Host Interface, or Serial Communications Interface MOTOROLA DSP56002/D, Rev. 3 iii Features Peripheral and Support Circuits • • Byte-wide host interface (HI) with Direct Memory Access (DMA) support (or fifteen Port B GPIO lines) SSI support: – – – – • • • • • • • Supports serial devices with one or more industry-standard codecs, other DSPs, microprocessors, and Motorola-SPI-compliant peripherals Asynchronous or synchronous transmit and receive sections with separate or shared internal/external clocks and frame syncs Network mode using frame sync and up to 32 software-selectable time slots 8-bit, 12-bit, 16-bit, and 24-bit data word lengths SCI for full duplex asynchronous communications (or three additional Port C GPIO lines) One 24-bit timer/event counter (or one additional GPIO line) Double-buffered peripherals Up to twenty-five General Purpose Input/Output (GPIO) pins One non-maskable and two maskable external interrupt/mode control pins On-Chip Emulation (OnCE™) port for unobtrusive, processor speedindependent debugging Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer for the DSP core clock with a wide input frequency range (12.2 KHz to 80 MHz) Miscellaneous Features • • • Power-saving Wait and Stop modes Fully static, HCMOS design for specified operating frequency down to dc Three packages available: – – – 132-pin Plastic Quad Flat Pack (PQFP); 1.1 × 1.1 × 0.19 inches 144-pin Thin Quad Flat Pack (TQFP); 20 × 20 × 1.5 mm 132-pin Ceramic Pin Grid Array (PGA); 1.36 × 1.35 × 0.125 inches iv DSP56002/D, Rev. 3 MOTOROLA DSP56002 Product Documentation PRODUCT DOCUMENTATION The three documents listed in the following table are required for a complete description of the DSP56002 and are necessary to design properly with the part. Documentation is available from one of the following locations (see back cover for detailed information): • • • • A local Motorola distributor A Motorola semiconductor sales office A Motorola Literature Distribution Center The World Wide Web (WWW) Table 1 DSP56002 Documentation Name DSP56000 Family Manual DSP56002 User’s Manual DSP56002 Technical Data Description Detailed description of the DSP56000 family processor core and instruction set Detailed functional description of the DSP56002 memory configuration, operation, and register programming DSP56002 features list and physical, electrical, timing, and package specifications Order Number DSP56KFAMUM/AD DSP56002UM/AD DSP56002/D MOTOROLA DSP56002/D, Rev. 3 v Product Documentation vi DSP56002/D, Rev. 3 MOTOROLA SECTION 1 SIGNAL/PIN DESCRIPTIONS INTRODUCTION DSP56002 signals are organized into twelve functional groups, as summarized in Table 1-1. Table 1-1 Signal Functional Group Allocations Functional Group Power (VCCX) Ground (GNDX) PLL and Clock Address Bus Data Bus Bus Control Interrupt and Mode Control Host Interface (HI) Port Serial Communications Interface (SCI) Port Synchronous Serial Interface (SSI) Port Timer/Event Counter or General Purpose Input/Output (GPIO) On-Chip Emulation (OnCE) Port Note: 1. 2. 3. Number of Signals 16 24 7 16 Port A1 24 10 4 Port B2 Port C3 15 3 6 1 4 Detailed Description Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 1-6 Table 1-7 Table 1-8 Table 1-9 Table 1-10 Table 1-11 Table 1-12 Table 1-13 Port A signals define the External Memory Interface port. Port B signals are the HI signals multiplexed on the external pins with the GPIO signals. Port C signals are the SCI and SSI signals multiplexed on the external pins with the GPIO signals. Figure 1-1 is a diagram of DSP56002 signals by functional group. MOTOROLA DSP56002/D, Rev. 3 1-1 Signal/Pin Descriptions Introduction DSP56002 VCCP VCCCK VCCQ VCCA VCCD VCCC VCCH VCCS GNDP GNDCK GNDQ GNDA GNDD GNDC GNDH GNDS EXTAL XTAL CKOUT CKP PCAP PINIT PLOCK 4 3 3 2 Power Inputs: PLL Clock Output Internal Logic Address Bus Data Bus Bus Control HI SSI/SCI Grounds: PLL Clock Internal Logic Address Bus Data Bus Bus Control HI SSI/SCI Interrupt Interrupt/ Mode Control MODA MODB MODC RESET IRQA IRQB NMI Port B Host Interface (HI) Port1 8 3 H0–H7 HA0–HA2 HR/W HEN HREQ HACK PB0–PB7 PB8–PB10 PB11 PB12 PB13 PB14 Port C Serial Communications Interface (SCI) Port2 RXD TXD SCLK PC0 PC1 PC2 4 5 6 4 2 PLL and Clock Synchronous Serial Interface (SSI) Port2 16 24 External Address Bus External Data Bus Timer/ Event Counter 3 SC0–SC2 SCK SRD STD PC3–PC5 PC6 PC7 PC8 A0–A15 D0–D23 PS DS X/Y BS BR BG BN WT RD WR Note: TIO External Bus Control Status OnCE Port DSCK DSI DSO DR OS1 OS0 1. The Host Interface port signals are multiplexed with the Port B GPIO signals (PB0–PB15). 2. The SCI and SSI signals are multiplexed with the Port C GPIO signals (PC0–PC8). 3. Power and Ground lines are indicated for the 144-pin TQFP package. AA1081G Figure 1-1 Signals Identified by Functional Group 1-2 DSP56002/D, Rev. 3 MOTOROLA Signal/Pin Descriptions Power POWER Table 1-2 Power Power Names VCCP Description Analog PLL Circuit Power—This line is dedicated to the analog PLL circuits and must remain noise-free to ensure stable PLL frequency and performance. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the VCC power rail. Use a 0.1 µF capacitor and a 0.01 µF capacitor located as close as possible to the chip package to connect between the VCCP line and the GNDP line. Clock Output Power—This line supplies a quiet power source for the CKOUT output. Ensure that the input vo