(DS91C180 / DS91D180) Multipoint LVDS (M-LVDS) Line Driver/Receiver

DS91D180/DS91C180 Multipoint LVDS (M-LVDS) Line Driver/Receiver June 2006 DS91D180/DS91C180 Multipoint LVDS (M-LVDS) Line Driver/Receiver General Description The DS91D180 and DS91C180 are high-speed differential M-LVDS single drivers/receivers designed for multipoint applications with multiple drivers or receivers. Multipoint LVDS (M-LVDS) is a new bus interface standard (TIA/EIA-899) based on LVDS but including several enhancements to improve multipoint performance. M-LVDS devices have superior drive capability and can support up to 32 loads. Along with increased drive, M-LVDS devices are required to have a controlled edge rate to minimize reflections and EMI. The 1 nSec minimum edge rate is tolerant of stub lengths up to 2 inches in length. M-LVDS devices also have a very large common mode range for additional noise margin in heavily loaded and noisy backplane environments The DS91D180/DS91C180 driver input accepts LVTTL/ LVCMOS signals and converts them to differential M-LVDS signal levels. The DS91D180/DS91C180 receiver accepts low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL) and converts them to 3V LVCMOS signals. The DS91D180 has a M-LVDS type 1 receiver input with no offset.The DS91C180 receiver contains an M-LVDS ”type 2” failsafe circuit with an internal 100 mV offset that provides a LOW output for both short and open input conditions. Features n n n n n n n n n n Meets TIA/EIA-899 M-LVDS Standard Capable of driving 32 M-LVDS loads Controlled edge rates tolerant to stubs Wide Common Mode for Increased Noise Immunity DS91D180 has type 1 receiver input DS91C180 has type 2 Fail-safe support Up to 200 Mbps operation Industrial temperature range Single 3.3 V Supply 14L SOIC Package (JEDEC MS-012) Typical Application in AdvancedTCA Clock Distribution 20041930 © 2006 National Semiconductor Corporation DS200419 www.national.com DS91D180/DS91C180 Connection Diagram Logic Diagram 20041926 Top View Order Number DS91D180TMA, DS91C180TMA See NS Package Number M14A 20041925 Ordering Information Order Number DS91D180TMA DS91C180TMA Receiver Input type 1 type 2 Function Data (0V threshold receiver) Control (offset fail-safe receiver) Package Type SOIC/M14A SOIC/M14A M-LVDS Receiver Types The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built in offset that is 100mV greater then VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short circuits at the input will always result in the output stage being driven to a low logic state. 20041940 FIGURE 1. M-LVDS Receiver Input Thresholds www.national.com 2 DS91D180/DS91C180 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, VCC Control Input Voltages Driver Input Voltage Driver Output Voltages Receiver Input Voltages Receiver Output Voltage SOIC Package Derate SOIC Package Thermal Resistance θJA θJC Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 4 seconds) −0.3V to +4V −0.3V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) −1.8V to +4.1V −1.8V to +4.1V −0.3V to (VCC + 0.3V) 1.1 W 8.8 mW/˚C above +25˚C 113.7 ˚C/W 36.9 ˚C/W 150˚C −65˚C to +150˚C 260˚C ESD Ratings: (HBM 1.5kΩ, 100pF) (EIAJ 0Ω, 200pF) (CDM 0Ω, 0pF) ≥ 5 kV ≥ 1000 V ≥ 250 V Recommended Operating Conditions Min Supply Voltage, VCC Voltage at Any Bus Terminal (Separate or Common-Mode) Differential Input Voltage VID High Level Input Voltage VIH Low Level Input Voltage VIL Operating Free Air Temperature TA −40 +25 +85 ˚C 2.0 0 2.4 VCC 0.8 V V V 3.0 −1.4 Typ Max Units 3.3 3.6 +3.8 V V Maximum Package Power Dissipation at +25˚C Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3, 4, 8) Symbol M-LVDS Driver |VYZ| ∆VYZ VOS(SS) Differential output voltage magnitude Change in differential output voltage magnitude between logic states Steady-state common-mode output voltage RL = 50Ω, CL = 5pF Figure 2 and Figure 4 RL = 50Ω, CL = 5pF Figure 2 and Figure 3 (VOS(pp) @ 500KHz clock) 0 0 RL = 50Ω, CL = 5pF, CD = 0.5pF Figure 7 and Figure 8 (Note 9) VIH = 2.0V VIL = 0.8V IIN = -18 mA Figure 6 See Function Tables Type 1 Type 2 VIT− VOH VOL IOZ IOSR Negative-going differential input voltage threshold See Function Tables High-level output voltage Low-level output voltage TRI-STATE output current Short circuit Rrceiver output current (LVTTL Output) IOH = −8mA IOL = 8mA VO = 0V or 3.6V VO = 0V −10 -90 -48 Type 1 Type 2 −50 50 2.4 480 −50 0.3 0 143 2.4 2.4 1.2VSS −0.2VSS -15 -15 -1.5 -43 20 94 20 94 2.7 0.28 0.4 10 43 50 150 15 15 0 1.8 650 +50 2.1 +50 mV mV V mV mV V V V V µA µA V mA mV mV mV mV V V µA mA Parameter Conditions Min Typ Max Units |∆VOS(SS)| Change in steady-state common-mode output voltage between logic states VOS(PP) VY(OC) VZ(OC) VP(H) VP(L) IIH IIL VIKL IOS VIT+ Peak-to-peak common-mode output voltage Maximum steady-state open-circuit output voltage Voltage overshoot, low-to-high level output Voltage overshoot, high-to-low level output High-level input current (LVTTL inputs) Low-level input current (LVTTL inputs) Input Clamp Voltage (LVTTL inputs) Differential short-circuit output current Positive-going differential input voltage threshold Maximum steady-state open-circuit output voltage Figure 5 M-LVDS Receiver 3 www.national.com DS91D180/DS91C180 Electrical Characteristics Symbol IA, IY Parameter M-LVDS Bus (Input and Output) Pins (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3, 4, 8) Conditions VA,Y = 3.8V, VB,Z = 1.2V, DE = GND VA,Y = 0V or 2.4V, VB,Z = 1.2V, DE = GND VA,Y = −1.4V, VB,Z = 1.2V, DE = GND −20 −32 32 −20 −32 −4 +4 32 −20 −32 32 −20 −32 +20 +20 +20 Min Typ Max Units Receiver input or driver high-impedance output current 32 +20 µA µA µA µA µA µA µA µA µA µA µA µA µA IB, IZ Receiver input or driver high-impedance output current VB,Z = 3.8V, VA,Y = 1.2V, DE = GND VB,Z = 0V or 2.4V, VA,Y = 1.2V, DE = GND VB,Z = −1.4V, VA,Y = 1.2V, DE = GND IAB, IYZ IA(OFF), IY(OFF) Receiver input or driver high-impedance output differential current (IA − IB or IY − IZ) Receiver input or driver high-impedance output power-off current VA,Y = VB,Z, −1.4V ≤ V ≤ 3.8V, DE = GND VA,Y = 3.8V, VB,Z = 1.2V, DE = VCC = 1.5V VA,Y = 0V or 2.4V, VB,Z = 1.2V, DE = VCC = 1.5V VA,Y = −1.4V, VB,Z = 1.2V, DE = VCC = 1.5V IB(OFF), IZ(OFF) Receiver input or driver high-impedance output power-off current VB,Z = 3.8V, VA,Y = 1.2V, DE = VCC = 1.5V VB,Z = 0V or 2.4V, VA,Y = 1.2V, DE = VCC = 1.5V VB,Z = −1.4V, VA,Y = 1.2V, DE = VCC = 1.5V IAB(OFF), IYZ(OFF) C A, CB C Y, CZ CAB CYZ CA/B, CY/Z ICCD ICCZ ICCR ICCB Receiver input or driver high-impedance output power-off differential current (IA(OFF) − IB(OFF) or IY(OFF) − IZ(OFF)) Receiver input capacitance Driver output capacitance Receiver input differential capacitance Driver output differential capacitance Receiver input or driver output capacitance balance (CA/CB or CY/CZ) Driver Supply Current TRI-STATE Supply Current Receiver Supply Current Supply Current, Driver and Receiver Enabled VA,Y = VB,Z, −1.4V ≤ V ≤ 3.8V, VCC = 1.5V, DE = 1.5V VCC = OPEN −4 5.1 8.5 2.5 5.5 1.0 +4 µA pF pF pF pF SUPPLY CURRENT (VCC) RL = 50Ω, DE = VCC, RE = VCC DE = GND, RE = VCC DE = GND, RE = GND DE = VCC, RE = GND 17 7 14 20 29.5 9.0 18.5 29.5 mA mA mA mA www.national.com 4 DS91D180/DS91C180 Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 3, 8) Symbol DRIVER AC SPECIFICATION tPLH tPHL tSKD1 (tsk(p)) tSKD3 tTLH (tr) tTHL (tf) tPZH tPZL tPLZ tPHZ tJIT fMAX tPLH tPHL tSKD1 (tsk(p)) tSKD3 tTLH (tr) tTHL (tf) tPZH tPZL tPLZ tPHZ fMAX Differential Propagation Delay Low to High Differential Propagation Delay High to Low Pulse Skew |tPLHD − tPHLD| (Notes 5, 9) Part-to-Part Skew (Notes 6, 9) Rise Time (Note 9) Fall Time (Note 9) Enable Time (Z to Active High) Enable Time (Z to Active Low ) Disable Time (Active Low to Z) Disable Time (Active High to Z) Random Jitter, RJ (Note 9) Maximum Data Rate Propagation Delay Low to High Propagation Delay High to Low Pulse Skew |tPLHD − tPHLD| (Notes 5, 9) Part-to-Part Skew (Notes 6, 9) Rise Time (Note 9) Fall Time (Note 9) Enable Time (Z to Active High) Enable Time (Z to Active Low) Disable Time (Active Low to Z) Disable Time (Active High to Z) Maximum Data Rate 200 RL = 500Ω, CL = 15 pF Figure 14 and Figure 15 0.5 0.5 1.2 1.2 CL = 15 pF Figures 11, 12 and Figure 13 100MHz clock pattern (Note 7) 200 2.0 2.0 4.7 5.3 0.6 7.5 7.5 1.9 1.5 3.0 3.0 10 10 10 10 2.5 RL = 50Ω, CL = 5 pF, CD = 0.5 pF Figure 9 and Figure 10 1.0 1.0 1.8 1.8 RL = 50Ω, CL = 5 pF, CD = 0.5 pF Figure 7 and Figure 8 1.0 1.0 3.4 3.1 300 5.5 5.5 420 1.9 3.0 3.0 8 8 8 8 5.5 ns ns ps ns ns ns ns ns ns ns psrms Mbps ns ns ns ns ns ns ns ns ns ns Mbps Parameter Conditions Min Typ Max Units RECEIVER AC SPECIFICATION Note 1: “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. Note 3: All typicals are given for VCC = 3.3V and TA = 25˚C. Note 4: The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is u