(DS91C176 / DS91D176) Multipoint-LVDS (M-LVDS) Transceivers

DS91D176/DS91C176 Multipoint-LVDS (M-LVDS) Transceivers February 2007 DS91D176/DS91C176 Multipoint-LVDS (M-LVDS) Transceivers General Description The DS91C176 and DS91D176 are high-speed M-LVDS differential transceivers designed for multipoint applications with multiple drivers or receivers. Multipoint LVDS (M-LVDS) is a new bus interface standard (TIA/EIA-899) based on LVDS but including several enhancements to improve multipoint performance. M-LVDS devices have superior drive capability and can support up to 32 loads. Along with increased drive, M-LVDS devices are required to have a controlled edge rate to minimize reflections and EMI. The 1 nSec minimum edge rate is tolerant of stub lengths up to 2 inches in length. MLVDS devices also have a very large common mode range for additional noise margin in heavily loaded and noisy backplane environments. The DS91C176/DS91D176 are half-duplex transceivers that accept LVTTL/LVCMOS signals at the driver inputs and convert them to differential M-LVDS signal levels. The receiver inputs accept low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL) and convert them to 3V LVCMOS signals. The DS91D176 has a M-LVDS type 1 receiver input with no offset. The DS91C176 receiver contains an M-LVDS type 2 failsafe circuit with an internal 100 mV offset that provides a LOW output for both short and open input conditions. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Meets TIA/EIA-899 M-LVDS Standard Capable of driving 32 LVDS loads Controlled Edge Rates Tolerant to Stubs Wide Common Mode for Increased Noise Immunity DS91D176 has type 1 receiver input DS91C176 has type 2 receiver with fail-safe Up to 200 Mbps operation Industrial temperature range Single 3.3V supply 8-lead SOIC package Typical Application in AdvancedTCA Clock Distribution 20024630 © 2007 National Semiconductor Corporation 200246 www.national.com DS91D176/DS91C176 Connection and Logic Diagram 20024601 Top View Order Number DS91D176TMA, DS91C176TMA See NS Package Number M08A Ordering Information Order Number DS91D176TMA DS91C176TMA Receiver Input type 1 type 2 Function Data (0V threshold receiver) Control (100 mV offset fail-safe receiver) Package Type SOIC/M08A SOIC/M08A M-LVDS Receiver Types The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built in offset that is 100mV greater then VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short circuits at the input will always result in the output stage being driven to a low logic state. 20024640 FIGURE 1. M-LVDS Receiver Input Thresholds www.national.com 2 DS91D176/DS91C176 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, VCC −0.3V to +4V Control Input Voltages −0.3V to (VCC + 0.3V) Driver Input Voltage −0.3V to (VCC + 0.3V) Driver Output Voltages −1.8V to +4.1V Receiver Input Voltages −1.8V to +4.1V Receiver Output Voltage −0.3V to (VCC + 0.3V) Maximum Package Power Dissipation at +25°C SOIC Package 833 mW Derate SOIC Package 6.67 mW/°C above +25°C Thermal Resistance  θJA 150°C/W  θJC Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 4 seconds) 63°C/W 150°C −65°C to +150°C 260°C ESD Ratings: (HBM 1.5kΩ, 100pF) (EIAJ 0Ω, 200pF) (CDM 0Ω, 0pF) ≥ 8 kV ≥ 250 V ≥ 1000 V Recommended Operating Conditions Supply Voltage, VCC Voltage at Any Bus Terminal Min Typ Max Units 3.0 3.3 3.6 V −1.4 +3.8 V 2.4 VCC 0.8 +25 +85 V V V °C  (Separate or Common-Mode) Differential Input Voltage VID LVTTL Input Voltage High VIH 2.0 LVTTL Input Voltage Low VIL 0 Operating Free Air Temperature TA −40 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3, 4, 8) Symbol M-LVDS Driver |VAB| ΔVAB VOS(SS) Differential output voltage magnitude Change in differential output voltage magnitude between logic states Steady-state common-mode output voltage RL = 50Ω, CL = 5pF Figure 2 and Figure 4 RL = 50Ω, CL = 5pF Figure 2 and Figure 3 (VOS(PP) @ 500KHz clock) Figure 5 RL = 50Ω, CL = 5pF, CD = 0.5pF Figure 7 and Figure 8 (Note 9) VIH = 2.0V VIL = 0.8V IIN = -18mA Figure 6 See Function Tables See Function Tables IOH = −8mA IOL = 8mA VO = 0V or 3.6V −10 -48 Type 1 Type 2 VIT− VOH VOL IOZ IOSR Negative-going differential input voltage threshold High-level output voltage (LVTTL output) Low-level output voltage (LVTTL output) TRI-STATE output current Type 1 Type 2 −50 50 2.4 0 0 −0.2VS S Parameter Conditions Min 480 −50 0.3 0 Typ Max 650 Units mV mV V mV mV 0 1.8 +50 2.1 +50 |ΔVOS(SS)| Change in steady-state common-mode output voltage between logic states VOS(PP) VA(OC) VB(OC) VP(H) VP(L) IIH IIL VIKL IOS VIT+ Peak-to-peak common-mode output voltage Maximum steady-state open-circuit output voltage Maximum steady-state open-circuit output voltage Voltage overshoot, low-to-high level output Voltage overshoot, high-to-low level output High-level input current (LVTTL inputs) Low-level input current (LVTTL inputs) Input Clamp Voltage (LVTTL inputs) Differential short-circuit output current Positive-going differential input voltage threshold 135 2.4 2.4 1.2VSS V V V V -15 -15 -1.5 -43 20 94 20 94 2.7 0.28 15 15 43 50 150 μA μA V mA mV mV mV mV V M-LVDS Receiver 0.4 10 -90 V μA mA Short-circuit receiver output current (LVTTL output) VO = 0V 3 www.national.com DS91D176/DS91C176 Symbol IA Parameter Transceiver input/output current Conditions VA = 3.8V, VB = 1.2V VA = 0V or 2.4V, VB = 1.2V VA = −1.4V, VB = 1.2V Min Typ Max 32 Units µA µA µA µA µA µA M-LVDS Bus (Input and Output) Pins −20 −32 32 −20 −32 −4 +4 32 −20 −32 32 −20 −32 −4 9 9 5.7 1.0 +4 +20 +20 +20 +20 IB Transceiver input/output current VB = 3.8V, VA = 1.2V VB = 0V or 2.4V, VA = 1.2V VB = −1.4V, VA = 1.2V IAB IA(OFF) Transceiver input/output differential current (IA − IB) VA = VB, −1.4V ≤ V ≤ 3.8V Transceiver input/output power-off current VA = 3.8V, VB = 1.2V, DE = VCC = 1.5V VA = 0V or 2.4V, VB = 1.2V, DE = VCC = 1.5V VA = −1.4V, VB = 1.2V, DE = VCC = 1.5V µA µA µA µA µA µA µA µA pF pF pF IB(OFF) Transceiver input/output power-off current VB = 3.8V, VA = 1.2V, DE = VCC = 1.5V VB = 0V or 2.4V, VA = 1.2V, DE = VCC = 1.5V VB = −1.4V, VA = 1.2V, DE = VCC = 1.5V IAB(OFF) CA CB CAB CA/B Transceiver input/output power-off differential current (IA(OFF) − IB(OFF)) Transceiver input/output capacitance Transceiver input/output capacitance Transceiver input/output differential capacitance Transceiver input/output capacitance balance (CA/ CB) Driver Supply Current TRI-STATE Supply Current Receiver Supply Current VA = VB, −1.4V ≤ V ≤ 3.8V, VCC = 1.5V, DE = 1.5V VCC = OPEN SUPPLY CURRENT (VCC) ICCD ICCZ ICCR RL = 50Ω, DE = VCC, RE = VCC DE = GND, RE = VCC DE = GND, RE = GND 20 6 14 29.5 9.0 18.5 mA mA mA www.national.com 4 DS91D176/DS91C176 Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 3, 8) Symbol DRIVER AC SPECIFICATION tPLH tPHL tSKD1 (tsk(p)) tSKD3 tTLH (tr) tTHL (tf) tPZH tPZL tPLZ tPHZ tJIT fMAX tPLH tPHL tSKD1 (tsk(p)) tSKD3 tTLH (tr) tTHL (tf) tPZH tPZL tPLZ tPHZ fMAX Differential Propagation Delay Low to High Differential Propagation Delay High to Low Pulse Skew |tPLHD − tPHLD| (Notes 5, 9) Part-to-Part Skew (Notes 6, 9) Rise Time (Note 9) Fall Time (Note 9) Enable Time (Z to Active High) Enable Time (Z to Active Low ) Disable Time (Active Low to Z) Disable Time (Active High to Z) Random Jitter, RJ (Note 9) Maximum Data Rate Propagation Delay Low to High Propagation Delay High to Low Pulse Skew |tPLHD − tPHLD| (Notes 5, 9) Part-to-Part Skew (Notes 6, 9) Rise Time (Note 9) Fall Time (Note 9) Enable Time (Z to Active High) Enable Time (Z to Active Low) Disable Time (Active Low to Z) Disable Time (Active High to Z) Maximum Data Rate 200 RL = 500Ω, CL = 15 pF Figure 14 and Figure 15 0.5 0.5 1.2 1.2 CL = 15 pF Figures 11, 12 and Figure 13 100 MHz Clock Pattern (Note 7) 200 2.0 2.0 4.7 5.3 0.6 7.5 7.5 1.7 1.3 2.5 2.5 10 10 10 10 2.5 RL = 50Ω, CL = 5 pF, CD = 0.5 pF Figure 9 and Figure 10 1.0 1.0 1.8 1.8 RL = 50Ω, CL = 5 pF, CD = 0.5 pF Figure 7 and Figure 8 1.3 1.3 3.4 3.1 300 5.0 5.0 420 1.3 3.0 3.0 8 8 8 8 5.5 ns ns ps ns ns ns ns ns ns ns psrms Mbps ns ns ns ns ns ns ns ns ns ns Mbps Parameter Conditions Min Typ Max Units RECEIVER AC SPECIFICATION Note 1: “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. Note 3: All typicals are given for VCC = 3.3V and TA = 25°C. Note 4: The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet. Note 5: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 6: tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. Note 7: Stimulus and fixture Jitter has been subtracted. Note 8: CL includes fixture capacitance a