Transmitter with built-in scaler for LVDS Display Interface (LDI)

DS90C2501 Transmitter with built-in scaler for LVDS Display Interface (LDI) October 2003 DS90C2501 Transmitter with built-in scaler for LVDS Display Interface (LDI) General Description The DS90C2501 is a highly integrated scaling IC with LVDS transmitter with a scaled resolution up to SXGA+ for single pixel input. The DS90C2501 is a video controller hub designed to be compatible with Graphic Memory Controller Hub (GMCH). The input interface can be single or dual DVO port (12 pin per port). The high quality cubic zoom engine scales the input graphics into the desired/optimal output resolution up to 1400x1050 resolution. Advanced video digital signal processing provides gamma correction, and dithering for the display output. A two-wire serial interface is used to communicate with the host system. The dual high speed LVDS channels supports single pixel in-single pixel out, single pixel in-dual pixel out, and dual pixel in-dual pixel out transmission modes. The DS90C2501 complies to Open LDI standard, and can be paired up with DS90CF388 receiver or FPD8531x/FPD8731x series integrated timing controller or FPDLink LVDS receivers such as DS90CF364/ DS90CF384A/DS90CF384/DS90CF384A. The LVDS output is similar to DS90C387 and DS90C387R. Thus, this transmitter can be paired up with DS90CF388, receiver of 112MHz LDI chipset or FPD-Link Receivers in non-DC Balance mode operation which provides GUI/LCD panel/mother board vendors a wide choice of inter-operation with LVDS based TFT panels. This chip is an ideal solution to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable industry standard interface based on LVDS technology that delivers the bandwidth needed for highresolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the “Applications Information” section of this datasheet. Features n Complies with Open LDI and GMCH DVO specification for digital display interfaces n 25 to 65 MHz clock in single pixel in to single pixel out operation. n 50 to 130 MHz clock in single pixel in to dual pixel out operation. n Support 24bit/48bit color TFT LCD with Conventional and Non-Conventional Color Mappings. n Support 16bit/32bit color TFT LCD. n Single pixel transmitter inputs support single pixel GUI interface. n Up scaling/panel fitting supports VGA to SXGA+ output in single pixel input mode at 640x480@60Hz, 800x600@60Hz, 1024x768@60Hz, 1280x1024@60Hz, 1400x1050@60Hz. n Independent horizontal and vertical scaling. n Support dithering (available for 6-bit color only), programmable smoothing and anti-aliasing filter. n Programmable digital sharpness, edge enhancement and contrast control via gamma correction. n Allow 2% at 200KHz spread spectrum clocking, rejects cycle-to-cycle jitter (+/− 20% of input data bit time). n Programmable LCD panel power sequencing. n Support low voltage swing signal level (1V to 1.8V), 2.5V and 3.3V LVTTL level on CLKINP, CLKINM, D0 to D23, DE, HSYNC and VSYNC pins n Support 2.5V/3.3V LVTTL level on configuration pins n Support 3.3V LVTTL level on GPIO pins n Available in 10mm x 10mm x 1mm 128pin thermally enhanced CSP package. n Two-wire serial communication interface is active during normal as well as power down mode and support data rates up to 400KHz. n TIA/EIA-644, Open LDI, DVO compliance. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. DVO is a registered trademark of Intel Corporation. AGP or 4x AGP is a registered trademark of Intel Corporation. © 2003 National Semiconductor Corporation DS200045 www.national.com DS90C2501 Block Diagram 20004552 www.national.com 2 DS90C2501 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Supply Voltage (VCC3V) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 sec.) +260˚C −0.3V to +2.8V −0.3V to +3.6V −0.3V to VCC3V −0.3V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) Continuous +150˚C −65˚C to +150˚C Typical Package Power Dissipation Capacity @ 70˚C and Max VCC 128 CSP Package: DS90C2501 Maximum Operating Case Temperature: 97˚C (measured at top center of package) ESD Rating: DS90C2501 (HBM, 1.5kΩ, 100pF) (EIAJ, 0Ω, 200pF) 1.8W > 2 kV > 250 V Recommended Operating Conditions Min Nom All Supply Voltage except (VCC3V) VCC3V Supply Voltage Operating Free Air Temperature (TA) Supply Noise Voltage (VCC) up to 33Mhz 2.250 2.5 3.0 0 3.3 +25 Max 2.750 3.6 +70 Units V V ˚C 100 mVP-P DC Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units LVCMOS/LVTTL DC SPECIFICATIONS (All input pins when operate in LVTTL level except DUAL pin. Note: On ID0, ID1 pins have typical 30K ohm internal pull-down, and ID2 and ID3 pins have typical 3K ohm internal pull-down.) VIH VIL VCL IIN High Level Input Voltage Low Level Input Voltage Input Clamp Voltage Input Current VREF = VCC3V VREF = VCC3V ICL = 18 mA VIN = 0.4V, or VCC VIN = GND LVCMOS/LVTTL DC SPECIFICATIONS for DUAL pin, pin35 VIH DUAL High Level Input Voltage (for dual pixel in to dual pixel out). PD = VCC3V 2.0 VCC V −15 2.0 -0.3 -0.9 +1.8 0 VCC3V 0.8 -1.5 +15 V V V µA µA VIM DUAL High Level Input Voltage (for single pixel in to dual pixel out). VIL DUAL High Level Input Voltage (for single pixel in to single pixel out). Input Clamp Voltage Input Current PD = VCC3V 1 ⁄2VCC−0.1 1 ⁄2VCC 1 ⁄2VCC+0.1 V PD = VCC3V 0 0.4 V VCL IIN ICL = 18 mA VIN = 0.4V, VCC VIN = Gnd -15 -0.9 1.8 0 0.1 -1.5 15 V µA µA LVCMOS/LVTTL DC SPECIFICATIONS for MSEN, pin 98 VOL Low level Open Drain Output IOL = 2 mA Voltage High Level Input Voltage Low Level Input Voltage Output Short Circuit Current VOUT = 0V IOL = 2 mA 2.2 0.3 V LVCMOS/LVTTL DC SPECIFICATIONS (Pin 62 to pin 69 when operate in 3.3V LVTTL level) VOH VOL IOS 2.95 0.055 -50 0.4 −120 V V mA 3 www.national.com DS90C2501 DC Characteristics Symbol VDDQ VILSH VILSL VREF Parameter Low Swing Voltage (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Conditions from GMCH Min 1 VREF+ 100mV 0 0.475 1 Typ Max +1.8 VDDQ VREF100mV Units V V V V Low Voltage Level DC SPECIFICATIONS (pins D0 to D23, CLKINP, CLKINM, DE, HSYNC,VSYNC) Low Swing High Level Input Voltage Low Swing Low Level Input Voltage Differential Input Reference Voltage Differential Output Voltage Change in VOD between Complimentary Output States Offset Voltage Change in VOS between Complimentary Output States Output Short Circuit Current Output TRI-STATE Current Transmitter Supply Current when data input and clock input are at Low Swing level. VOUT = 0V PD = 0V, VOUT = 0V or VCC RL = 100Ω, CL = 5 pF, DUAL pin = GND, BAL = GND, one 12bit input, Pattern Figure 1 RL = 100Ω, CL = 5 pF, DUAL pin = 1⁄2 VCC, BAL = GND, one 12bit input, Pattern Figure 1 RL = 100Ω, CL = 5 pF, DUAL pin = GND, BAL = GND, one 12bit input RL = 100Ω, CL = 5 pF, DUAL pin = 1⁄2VCC, BAL = GND, one 12bit input f = 65MHz, scaler off, 2.75V supply f = 65 MHz, scaler off, 3.6V supply f = 108MHz, scaler off, 2.75V supply f = 108 MHz, scaler off, 3.6V supply. f = 65 MHz, scaler on, 2.75V supply 0 1.125 RL = 100Ω ⁄2VDDQ 0.945 LVDS DRIVER DC SPECIFICATIONS (Output pins AnP, AnM, CLKnP and CLKnM) VOD ∆VOD 250 345 3 450 35 mV mV VOS ∆VOS 1.32 1.5 1.475 35 V mV IOS IOZ ICC1 −8.5 -15 mA µA mA ±0.1 70 ±10 120 SUPPLY CURRENT 38 90 mA ICC2 Transmitter Supply Current when data input and clock input are at Low Swing level. 85 130 mA 75 130 mA ICC3 Transmitter Supply Current when data input and clock input are at Low Swing level. 330 415 mA ICC4 Transmitter Supply Current when data input and clock input are at Low Swing level. f = 108 MHz, scaler on, 2.75V supply 483 610 mA ICCTZ Transmitter Supply Current Power Down PD = GND. TST1, TST2, TST3, ID0, ID1, ID2, ID3, A0, A1, A2, RES1, RES2, RES3, RES4 = GND, BAL = GND. 75 µA www.national.com 4 DS90C2501 Two-Wire Serial Communication Interface Unless otherwise noted, below specifications apply for VCC3V pin = 3.0V to 3.6V. Symbol VIN(1) VIN(0) VOL Parameter Logical “ 1 ” input voltage Logical “ 0 ” input voltage Serial Bus Low level output voltage IOL = 3mA IOL = 6mA 0.1 0.15 Conditions Min 2.1 0.8 0.4 0.6 Typ Max Units V V V V Recommended DVO Port Input Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol TCIT TCIP TCIH TCIL TXIT VDDQ TxCLK IN Period (Figure 5) TxCLK in High Time (Figure 5) TxCLK in Low Time (Figure 5) D0 to D23 Transition Time Low Swing Voltage Amplitude from GMCH 1.0 Parameter TxCLK IN Transition Time (Figure 4) DUAL = Gnd DUAL = Gnd Min 0.8 5.9 0.35T 0.35T Typ 1.2 T 0.5T 0.5T 1 1.8 Max 2.4 40 0.65T 0.65T Units ns ns ns ns ns V 5 www.national.com DS90C2501 AC Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol LLHT LHLT TBIT Parameter LVDS Low-to-High Transition Time (Figure 3). (Note 7) LVDS High-to-Low Transition Time (Figure 3). (Note 7) Transmitter Output Bit Width DUAL pin = VCC or Gnd DUAL pin = 1⁄2VCC TCCS TPPOS0 TxOUT Channel to Channel Skew Transmitter Output Pulse Position for Bit 0 (previous cycle) from CLK1P rising edge (Note 7). Transmitter Output Pulse Position for Bit1 (previous cycle) from CLK1P rising edge. (Note 7) Transmitter Output Pulse Position for Bit2 from CLK1P rising edge. (Note 7) Transmitter Output Pulse Position for Bit3 from CLK1P rising edge. (Note 7) Transmitter Output Pulse Position for Bit4 from CLK1P rising edg