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DS3100 Stratum 3/3E Timing Card IC
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GENERAL DESCRIPTION
When paired with an external TCXO or OCXO, the DS3100 is a complete central timing and synchronization solution for SONET/SDH network elements. With two multiprotocol BITS/SSU receivers and 14 input clocks, the device directly accepts both external timing and line timing from a large number of line cards. All input clocks are continuously monitored for frequency accuracy and activity. Any two of the input clocks can be selected as the references for the two core DPLLs. The T0 DPLL complies with the Stratum 3 and 3E requirements of GR1244, GR-253, and the requirements of G.812 Type III and G.813. From the output of the core DPLLs, a wide variety of output clock frequencies and frame pulses can be produced simultaneously on the 11 output clock pins. Two DS3100 devices can be configured in a master/slave arrangement for timing card equipment protection. The DS3100 registers and I/O pins are backward compatible with Semtech’s ACS8520 and ACS8530 timing card ICs.
FEATURES
Synchronization Subsystem for Stratum 3E, 3, 4E and 4, SMC and SEC - Meets Requirements of GR-1244 Stratum 3/3E, GR-253, G.812 Types I, III and IV, and G.813 - Stratum 3E Holdover Accuracy with Suitable External Oscillator - Programmable Bandwidth, 0.5mHz to 70Hz - Hitless Reference Switching on Loss of Input - Phase Build-Out and Transient Absorption - Locks to and Generates 125MHz for Gigabit Synchronous Ethernet per ITU-T G.8261 14 Input Clocks - 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any Multiple of 8kHz Up to 125MHz - Two LVDS/LVPECL/CMOS/TTL Inputs Accept Nx8kHz Up to 125MHz Plus 155.52MHz - Two 64kHz Composite Clock Receivers - Continuous Input Clock Quality Monitoring - Separate 2/4/8kHz Frame Sync Input 11 Output Clocks - Five CMOS/TTL Outputs Drive Any Internally Produced Clock Up to 77.76MHz - Two LVDS Outputs Each Drive Any Internally Produced Clock Up to 311.04MHz - One 64kHz Composite Clock Transmitter - One 1.544MHz/2.048MHz Output Clock - Two Sync Pulses: 8kHz and 2kHz - Output Clock Rates Include 2kHz, 8kHz, NxDS1, NxDS2, DS3, NxE1, E3, 6.48MHz, 19.44MHz, 38.88MHz, 51.84MHz, 62.5MHz, 77.76MHz, 125MHz, 155.52MHz, 311.04MHz Two Multiprotocol BITS/SSU Transceivers - Receive and Transmit DS1, E1, 2048kHz, and 6312kHz Timing Signals - Insert and Extract SSM Messages (DS1, E1) - Automatically Invalidate Clocks on LOS, OOF, AIS, and Other Defects Internal Compensation for Master Clock Oscillator Frequency Accuracy Processor Interface: 8-Bit Parallel or SPI Serial 1.8V Operation with 3.3V I/O (5V Tolerant)
APPLICATIONS
SONET/SDH ADMs, MSPPs, and MSSPs Digital Cross-Connects DSLAMs Service Provider Routers
FUNCTIONAL DIAGRAM
TIMING FROM LINE CARDS (VARIOUS RATES) 14 TIMING FROM BITS/SSU (DS1, E1, CC, ETC.) LOCAL TCXO OR OCXO TIMING TO BITS/SSU (DS1, E1, CC, ETC.)
DS3100
SONET/SDH SYNCHRONIZATION IC
2
2
11
TIMING TO LINE CARDS (VARIOUS RATES)
CONTROL STATUS
ORDERING INFORMATION
PART DS3100GN DS3100GN+ TEMP RANGE -40°C to +85°C -40°C to +85°C PIN-PACKAGE 256 CSBGA (17mm) 2 256 CSBGA (17mm) 2
+Denotes a lead-free package.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 060607
DS3100 Stratum 3/3E Timing Card IC
TABLE OF CONTENTS
1. STANDARDS COMPLIANCE ................................................................................................7 2. BLOCK DIAGRAM.................................................................................................................8 3. APPLICATION EXAMPLE .....................................................................................................9 4. DETAILED DESCRIPTION ..................................................................................................10 5. DETAILED FEATURES .......................................................................................................12
5.1 5.2 5.3 5.4 5.5 5.6 T0 DPLL FEATURES....................................................................................................................12 T4 DPLL FEATURES....................................................................................................................12 INPUT CLOCK FEATURES .............................................................................................................12 OUTPUT CLOCK FEATURES ..........................................................................................................13 REDUNDANCY FEATURES .............................................................................................................13 BITS TRANSCEIVER FEATURES....................................................................................................13
5.6.1 5.6.2 5.6.3 General......................................................................................................................................... 13 Receiver ....................................................................................................................................... 13 Transmitter ................................................................................................................................... 14
5.7 5.8
COMPOSITE CLOCK I/O FEATURES...............................................................................................14 GENERAL FEATURES ...................................................................................................................14
6. PIN DESCRIPTIONS............................................................................................................15 7. FUNCTIONAL DESCRIPTION .............................................................................................24
7.1 7.2 7.3 7.4 7.5 OVERVIEW ..................................................................................................................................24 DEVICE IDENTIFICATION AND PROTECTION ...................................................................................25 LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION ...........................................................25 INPUT CLOCK CONFIGURATION ....................................................................................................26
7.4.1 7.4.2 7.5.1 7.5.2 7.5.3 7.5.4 Signal Format Configuration......................................................................................................... 26 Frequency Configuration .............................................................................................................. 28 Frequency Monitoring................................................................................................................... 29 Activity Monitoring ........................................................................................................................ 29 Selected Reference Activity Monitoring ....................................................................................... 30 Composite Clock Inputs ............................................................................................................... 30 Priority Configuration.................................................................................................................... 31 Automatic Selection Algorithm ..................................................................................................... 31 Forced Selection .......................................................................................................................... 32 Ultra-Fast Reference Switching.................................................................................................... 32 External Reference Switching Mode ............................................................................................ 32 Output Clock Phase Continuity During Reference Switching ...................................................... 33 T0 DPLL State Machine ............................................................................................................... 33 T4 DPLL State Machine ............................................................................................................... 36 Bandwidth..................................................................................................................................... 37 Damping Factor............................................................................................................................ 38 Phase Detectors........................................................................................................................... 38 Loss of Phase Lock Detection...................................................................................................... 39 Phase Monitor and Phase Build-Out............................................................................................ 40 Input to Output Phase Adjustment ............................................................................................... 41 Phase Recalibration ..................................................................................................................... 41 Frequency and Phase Measurement ........................................................................................... 41 Input Wander and Jitter Tolerance ............................................................................................... 42 2 of 226
INPUT CLOCK QUALITY MONITORING ............................................................................................29
7.6
INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING ..................................................................31
7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6
7.7
DPLL ARCHITECTURE AND CONFIGURATION ...........................
