SMBus Silicon Serial Number

DS28CM00 I²C/SMBus Silicon Serial Number www.maxim-ic.com GENERAL DESCRIPTION The DS28CM00 is a low-cost, electronic registration number to provide an absolutely unique identity that can be determined with the industry standard I²C and SMBus interface. The registration number is a factory-lasered, 64-bit ROM that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit family code (70h). In SMBus mode, the DS28CM00 resets its communication interface if it detects a bus fault condition. FEATURES Unique, Factory-Lasered and Tested 64-bit Registration Number (8-bit Family Code + 48-bit Serial Number + 8-bit CRC) SMBus-Compatible I²C Serial Interface Supports 100kHz and 400kHz Communication Speeds 5V Tolerant Interface Pins Operating Range: 1.8V ±10% to 5V ±5%, -40°C to +85°C 5-Pin SOT23 Package APPLICATIONS Printed Circuit Board Unique Serialization Accessory and Peripheral Identification Equipment Registration and License Management Network Node Identification ORDERING INFORMATION PART DS28CM00R-A00+T TEMP RANGE -40°C to +85°C PIN-PACKAGE SOT23-5 Tape-and-Reel +Denotes lead-free package. www.DataSheet4U.com TYPICAL OPERATING CIRCUIT VCC RP VCC SDA SCL RP PIN CONFIGURATION SCL GND SDA 1 2 3 4 NC 5 VCC µC GND VCC SDA SCL DS28CM00 GND SOT23 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 9 REV: 072406 DS28CM00: I²C/SMBus Silicon Serial Number ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Maximum Current Into Any Pin Operating Temperature Range Junction Temperature Storage Temperature Range Soldering Temperature -0.5V, +6V ±20mA -40°C to +85°C +150°C -55°C to +125°C See IPC/JEDEC J-STD-020 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device. ELECTRICAL CHARACTERISTICS (-40°C to +85°C, see Note 1) PARAMETER Supply Voltage Standby Current Operating Current SYMBOL VCC ICCS ICCA CONDITIONS Bus idle, VCC = 5.25V Bus active at 400kHz, VCC = 5.25V VCC ≥ 2.0V LOW Level Input Voltage VIL VCC < 2.0V HIGH Level Input Voltage (Note 3) VCC ≥ 2.0V VIH VCC < 2.0V VCC ≥ 2.0V Vhys VCC < 2.0V VOL VCC ≥ 2.0V tof VCC < 2.0V tSP Ii Ci fSCL tTIMEOUT tHD:STA SDA and SCL pins only (Note 4) (Note 6) (Note 4) VCC ≥ 2.0V VCC < 2.0V (Note 7) (Note 8) VCC ≥ 2.7V VCC ≥ 2.0V VCC < 2.0V (Note 8) (Note 8) 2 of 9 -10 20 + 0.1Cb 20 + 0.1Cb -0.3 0.7 × VCC 0.8 × VCC 0.05 × VCC 0.1 × VCC MIN 1.62 TYP MAX 5.25 3 200 UNITS V µA µA SCL, SDA Pins (Note 2) See Figure 5 -0.3 0.3 × VCC 0.25 × VCC VCCmax + 0.3V VCCmax + 0.3V V V Hysteresis of Schmitt Trigger Inputs (Note 4) LOW Level Output Voltage at 4mA Sink Current Output Fall Time from VIhmin to VILmax with a Bus Capacitance from 10pF to 400pF (Notes 4, 5) Pulse Width of Spikes that are Suppressed by the Input Filter Input Current with an Input Voltage Between 0.1VCC and 0.9VCCmax Input Capacitance SCL Clock Frequency (Note 7) Bus Time-out Hold Time (Repeated) START Condition. After this Period, the First Clock Pulse is Generated. LOW Period of the SCL Clock (Note 8) HIGH Period of the SCL Clock Setup Time for a Repeated START Condition V 0.4 250 V ns 450 50 10 10 400 344 75 ns µA pF kHz ms µs 25 0.6 1.3 1.5 2.3 0.6 0.6 tLOW tHIGH tSU:STA µs µs µs DS28CM00: I²C/SMBus Silicon Serial Number PARAMETER Data Hold Time (Notes 9, 10) Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Capacitive Load for Each Bus Line SYMBOL tHD:DAT tSU:DAT tSU:STO tBUF Cb CONDITIONS VCC ≥ 2.7V VCC ≥ 2.0V VCC < 2.0V (Notes 8, 11) (Note 8) (Note 8) (Notes 4, 8) MIN 0.3 0.3 0.3 100 0.6 1.3 400 TYP MAX 0.9 1.1 1.7 UNITS µs ns µs µs pF Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Specifications at -40°C are guaranteed by design and characterization only and not production tested. All values are referred to VIHmin and VILmax levels. The maximum specification value is guaranteed by design, not production tested. Not production tested. Guaranteed by design or characterization. CB = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according to I2C-Bus Specification v2.1 are allowed. The DS28CM00 does not obstruct the SDA and SCL lines if VCC is switched off. The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1 AND SCL stays at the same logic level or SDA stays low for this interval, the DS28CM00 behaves as though it has sensed a STOP condition. System Requirement The DS28CM00 provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal. A Fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement tSU:DAT ≥ 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tSU:DAT = 1000 + 250 = 1250ns (according to the standard-mode I²C-bus specification) before the SCL line is released. PIN DESCRIPTION PIN 1 2 3 4 5 NAME SCL GND SDA N.C. VCC FUNCTION Serial interface clock input; must be tied to VCC through a pullup resistor. 5V tolerant input over 1.62V to 5.25V VCC range. Ground supply for the device. Serial interface bi-directional data line; must be tied to VCC through a pullup resistor. 5V tolerant input/output over 1.62V to 5.25V VCC range. Not Connected Power Supply Input OVERVIEW The DS28CM00 consists of a serial interface which provides access to a unique 64-bit Registration number and a Control Register, as shown in the block diagram in Figure 1. The device communicates with a host processor through its SMBus compatible I²C bus interface in standard-mode or in fast-mode. Since the network address of the DS28CM00 is fixed, exactly one device can reside on a bus segment. The Registration Number and Control Register are located in a linear 9-byte address space (Figure 2). 3 of 9 DS28CM00: I²C/SMBus Silicon Serial Number Figure 1. Block Diagram VCC SCL SDA Serial Interface ROM Registration Number Control Register GND Figure 2. Memory Map ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h TYPE ROM ROM ROM ROM ROM ROM ROM ROM SRAM ACCESS Read Read Read Read Read Read Read Read R/W DESCRIPTION Device Family Code (70h) Serial Number, bits 0 to 7 Serial Number, bits 8 to 15 Serial Number, bits 16 to 23 Serial Number, bits 24 to 31 Serial Number, bits 32 to 39 Serial Number, bits 40 to 47 CRC of Family Code and 48-bit Serial Number Control Register Unique Registration Number Each DS28CM00 has a unique Registration Number that is 64 bits long. The registration number begins with the family code at address 00h followed by the 48-bit serial number (LS-byte at the lower address) and ends at address 07h with the CRC (Cyclic Redundancy Check) of the first 56 bits. This CRC is generated using the polynomial X8 + X5 + X4 + 1. Additional information about CRCs is available in Application Note 27. The ROM Registration Number is not related to the I²C slave address of the device. Control Register The Control Register at address 08h allows switching between I²C mode and SMBus mode. Only the LS bit of this register, referred to as the CM bit, has a function. The other 7 bits always read 0 and cannot be changed. When the CM bit is set to 1 (power-on default), the device is in SMBus mode, which enables the bus timeout function. Setting the CM bit to 0 puts the device in I²C mode, where the timeout function is disabled. In SMBus mode, the serial interface times out and is internally reset if SCL is stuck (high or low) or if SDA is stuck low for the duration of tTIMEOUT or longer. This reset turns the SDA line into an input, ensuring that the device is ready to recognize a communication start condition. ADDR 08h b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 CM 4 of 9 DS28CM00: I²C/SMBus Silicon Serial Number DEVICE OPERATION Typically, the DS28CM00 is accessed after power-up to read the 64-bit Registration number, which may serve to identify the object that the device is embedded in. Write access exists only to the Control Register. Read and write access are controlled through the I²C/SMBus serial interface. See section Read and Write for details. Serial Communication Interface General Characteristics The serial interface uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage through a pullup resistor. When there is no communication, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data can be transferred at rates of up to 100kbps in the Standard-mode, up to 400kbps in the Fast-mode. The DS28CM00 works in both modes. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the communication is called a “master.” The devices that are controlled by the master are “slaves.” The DS28CM00 is a slave device. Slave Address/Direction Byte To be individually accessed, each device must have a slave address that does not conflict