Quad Transceiver

DS25BR400 Quad Transceiver with Input Equalization and Output De-Emphasis May 2006 DS25BR400 Quad Transceiver with Input Equalization and Output De-Emphasis General Description The DS25BR400 is a quad 250 Mbps – 2.5 Gbps CML transceiver, or 8-channel buffer, for use in XAUI Fibre Channel backplane and cable applications. With operation down to 250 Mbps, the DS25BR400 can be used in applications requiring both low and high frequency data rates. Each input stage has a fixed equalizer to reduce ISI distortion from board traces. The equalizers are grouped in fours and are enabled through two control pins. These control pins provide customers flexibility in XAUI applications where ISI distortion may vary from one direction to another. All output drivers have four selectable steps of de-emphasis to compensate against transmission loss across long FR4 backplanes. The de-emphasis blocks are also grouped in fours. In addition, the DS25BR400 also has loopback control capability on four channels. All CML drivers and receivers are internally terminated with 50Ω pull-up resistors. Features n Quad 2.5 Gbps Transceiver or 8-Channel CML Serial Buffer n 250 Mbps – 2.5 Gbps Fully Differential Data Paths n Optional Fixed Input Equalization n Selectable Output De-emphasis n Individual Loopback Controls n On-chip Termination n +3.3V supply n Low Power, 1.3 Watts MAX n Lead-less eLLP-60 pin package (9mmx9mmx0.8mm, 0.4mm pitch) n −40˚C to +85˚C Industrial Temperature Range n 6 kV ESD Rating, HBM Functional Block Diagram 20194201 © 2006 National Semiconductor Corporation DS201942 www.national.com DS25BR400 Connection Diagram 20194202 Leadless eLLP-60 Pin Package (9mmx9mmx0.8mm, 0.4mm pitch) Order number DS25BR400TSQ See NS Package Number SQA060 www.national.com 2 DS25BR400 Pin Descriptions Pin Name Pin Number 51 52 48 49 43 42 40 39 33 34 36 37 25 24 28 27 58 57 55 54 6 7 3 4 10 9 13 12 18 19 21 28 60 I/O Description DIFFERENTIAL I/O IB_0+ IB_0− OA_0+ OA_0− IB_1+ IB_1− OA_1+ OA_1− IB_2+ IB_2− OA_2+ OA_2− IB_3+ IB_3− OA_3+ OA_3− IA_0+ IA_0− OB_0+ OB_0− IA_1+ IA_1− OB_1+ OB_1− IA_2+ IA_2− OB_2+ OB_2− IA_3+ IA_3− OB_3+ OB_3− EQA I O I O I O I O I O I O I O I O Inverting and non-inverting differential inputs of port_0. IB_0+ and IB_0− are internally connected to a reference voltage through a 50Ω resistor. Inverting and non-inverting differential outputs of port_0. OA_0+ and OA_0− are connected to VCC through a 50Ω resistor. Inverting and non-inverting differential inputs of port_1. IB_1+ and IB_1− are internally connected to a reference through a 50Ω resistor. Inverting and non-inverting differential outputs of port_1. OA_1+ and OA_1− are connected to VCC through a 50Ω resistor. Inverting and non-inverting differential inputs of port_2. IB_2+ and IB_2− are internally connected to a reference voltage through a 50Ω resistor. Inverting and non-inverting differential outputs of port_2. OA_2+ and OA_2− are connected to VCC through a 50Ω resistor. Inverting and non-inverting differential inputs of port_3. IB_3+ and IB_3− are internally connected to a reference voltage through a 50Ω resistor. Inverting and non-inverting differential outputs of port_3. OA_3+ and OA_3− are connected to VCC through a 50Ω resistor. Inverting and non-inverting differential inputs of port_0. IA_0+ and IA_0− are internally connected to a reference voltage through a 50Ω resistor. Inverting and non-inverting differential outputs of port_0. OB_0+ and OB_0− are connected to VCC through a 50Ω resistor. Inverting and non-inverting differential inputs of port_1. IA_1+ and IA_1− are internally connected to a reference through a 50Ω resistor. Inverting and non-inverting differential outputs of port_1. OB_1+ and OB_1− are connected to VCC through a 50Ω resistor. Inverting and non-inverting differential inputs of port_2. IA_2+ and IA_2− are internally connected to a reference voltage through a 50Ω resistor. Inverting and non-inverting differential outputs of port_2. OB_2+ and OB_2− are connected to VCC through a 50Ω resistor. Inverting and non-inverting differential inputs of port_3. IA_3+ and IA_3− are internally connected to a reference voltage through a 50Ω resistor. Inverting and non-inverting differential outputs of port_3. OB_3+ and OB_3− are connected to VCC through a 50Ω resistor. This pin is active LOW. A logic LOW at EQA enables equalization for input channels IA_0 ± , IA_1 ± , IA_2 ± , and IA_3 ± . By default, this pin is internally pulled high and equalization is disabled. This pin is active LOW. A logic LOW at EQB enables equalization for input channels IB_0 ± , IB_1 ± , IB_2 ± , and IB_3 ± . By default, this pin is internally pulled high and equalization is disabled. PreA_0 and PreA_1 select the output de-emphasis levels (OA_0 ± , OA_1 ± , OA_2 ± , and OA_3 ± ). PreA_0 and PreA_1 are internally pulled high. Please see Table 2 for de-emphasis levels. PreB_0 and PreB_1 select the output de-emphasis levels (OB_0 ± , OB_1 ± , OB_2 ± , and OB_3 ± ). PreB_0 and PreB_1 are internally pulled high. Please see Table 2 for de-emphasis levels. This pin is active LOW. A logic LOW at LB0 enables the internal loopback path from IB_0 ± to OA_0 ± . LB0 is internally pulled high. Please see Table 1 for more information. This pin is active LOW. A logic LOW at LB1 enables the internal loopback path from IB_1 ± to OA_1 ± . LB1 is internally pulled high. Please see Table 1 for more information. CONTROL (3.3V LVCMOS) I EQB 16 I PreA_0 PreA_1 PreB_0 PreB_1 LB0 LB1 15 1 31 45 46 44 I I I I 3 www.national.com DS25BR400 Pin Descriptions Pin Name Pin Number 32 30 59 (Continued) I/O Description CONTROL (3.3V LVCMOS) LB2 LB3 RSV POWER VCC 5, 11, 20, 26, 35, 41, 50, 56 P VCC = 3.3V ± 5%. Each VCC pin should be connected to the VCC plane through a low inductance path, typically with a via located as close as possible to the landing pad of the VCC pin. It is recommended to have a 0.01 µF or 0.1 µF, X7R, size-0402 bypass capacitor from each VCC pin to ground plane. Ground reference. Each ground pin should be connected to the ground plane through a low inductance path, typically with a via located as close as possible to the landing pad of the GND pin. DAP is the metal contact at the bottom side, located at the center of the eLLP-60 pin package. It should be connected to the GND plane with at least 4 via to lower the ground impedance and improve the thermal performance of the package. I I I This pin is active LOW. A logic LOW at LB2 enables the internal loopback path from IB_2 ± to OA_2 ± . LB2 is internally pulled high. Please see Table 1 for more information. This pin is active LOW. A logic LOW at LB3 enables the internal loopback path from IB_3 ± to OA_3 ± . LB3 is internally pulled high. Please see Table 1 for more information. Reserve pin to support factory testing. This pin can be left open, tied to GND, or tied to GND through an external pull-down resistor. GND 8, 14, 23, 29, 38, 47, 53 DAP P GND P Note: I = Input, O = Output, P = Power www.national.com 4 DS25BR400 Functional Description TABLE 1. Logic Table for Loopback Controls LB0 0 1 (default) LB1 0 1 (default) LB2 0 1 (default) LB3 0 1 (default) Loopback Function Enable loopback from IB_0 ± to OA_0 ± . Normal mode. Loopback disabled. Loopback Function Enable loopback from IB_1 ± to OA_1 ± . Normal mode. Loopback disabled. Loopback Function Enable loopback from IB_2 ± to OA_2 ± . Normal mode. Loopback disabled. Loopback Function Enable loopback from IB_3 ± to OA_3 ± . Normal mode. Loopback disabled. TABLE 2. De-Emphasis Controls PreA_[1:0] 00 01 10 1 1 (Default) PreB_[1:0] 00 01 10 1 1 (Default) Default VOD Level in mVPP (VODB) 1200 1200 1200 1200 Default VOD Level in mVPP (VODB) 1200 1200 1200 1200 De-Emphasis Level in mVPP (VODPE) 1200 850 600 426 De-Emphasis Level in mVPP (VODPE) 1200 850 600 426 De-Emphasis in dB (VODPE/VODB) 0 −3 −6 −9 De-Emphasis in dB (VODPE/VODB) 0 −3 −6 −9 De-emphasis is the primary signal conditioning function for use in compensating against backplane transmission loss. The DS25BR400 provides four steps of de-emphasis ranging from 0, −3, −6 and −9 dB, user-selectable dependent on the loss profile of the backplane. Figure 1 shows a driver de-emphasis waveform. The de-emphasis duration is nominal 188 ps, corresponding to 0.75 bit-width at 2.5 Gbps. The de-emphasis levels of switch-side and line-side can be individually programmed. 5 www.national.com DS25BR400 Input Equalization Each differential input of the DS25BR400 has a fixed equalizer front-end stage. It is designed to provide fixed equalization for short board traces with transmission losses of approximately 5 dB between 375 MHz to 1.875 GHz. Programmable de-emphasis together with input equalization ensures an acceptable eye opening for a 40-inch FR-4 backplane. The differential input equalizer for inputs on Channel A and inputs on Channel B can be bypassed by using EQA and EQB, respectively. By default, the equalizers are internally pulled high and disabled. Therefore, EQA and EQB must be asserted LOW to enable equalization. 20194237 FIGURE 1. Driver De-Emphasis Differential Waveform (showing all 4 de-emphasis steps) www.national.com 6 DS25BR400 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) CMOS/TTL Input Voltage CML Input/Output Voltage Junction Temperature Storage Temperature Lead Temperature Soldering, 4 sec Thermal Resistance, θJA Thermal Resistance, θJC −0.3V to 4V −0.3V to (VCC +0.3V) −0.3V to (VCC +0.3V) +150˚C −65˚C to +150˚C +260˚C 22.3˚C/W 3.2˚C/W Thermal Resistance, ΦJB (Note: assumes 26 thermal vias) ESD Ratings ((Note 9)) HBM CDM MM 10.3˚C/W 6kV