3.125 Gbps LVDS Buffer

DS25BR150 3.125 Gbps LVDS Buffer April 2007 DS25BR150 3.125 Gbps LVDS Buffer General Description The DS25BR150 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over printed circuit boards and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The DS25BR150 is a buffer/repeater with very low power consumption. Other LVDS devices with similar IO characteristics and with signal conditioning features include the following products. The DS25BR110 features four levels of equalization for use as an optimized receiver device, the DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR100 features both pre-emphasis and equalization for use as an optimized repeater device. Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce component count, and further minimize board space. Features ■ DC - 3.125 Gbps low jitter, high noise immunity, low power operation ■ On-chip 100 Ω input and output termination minimizes insertion and return losses, reduces component count and minimizes board space ■ 7 kV ESD on LVDS I/O pins protects adjoining components ■ Small 3 mm x 3 mm LLP-8 space saving package Applications ■ ■ ■ ■ ■ ■ ■ Clock or data buffering / repeating OC-48 / STM-16 Clock or data buffering / repeating Serial ATA (SATA-150 and SATA-300) Fibre Channel (2GFC) PCI Express InfiniBand FireWire Typical Application 30005510 © 2007 National Semiconductor Corporation 300055 www.national.com DS25BR150 Block Diagram 30005507 Pin Diagram 30005508 Pin Descriptions Pin Name NC IN+ INNC NC OUTOUT+ VCC GND Pin Name 1 2 3 4 5 6 7 8 DAP Pin Type NA Input Input NA NA Output Output Power Power Pin Description "NO CONNECT" pin. Non-inverting LVDS input pin. Inverting LVDS input pin. "NO CONNECT" pin. "NO CONNECT" pin. Inverting LVDS output pin. Non-inverting LVDS Output pin. Power supply pin. Ground pad (DAP - die attach pad) Ordering Codes and Configurations NSID DS25BR150TSD Function Buffer/Repeater www.national.com 2 DS25BR150 Absolute Maximum Ratings (Note 4) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +4V LVDS Input Voltage (IN+, IN−) −0.3V to +4V LVDS Differential Input Voltage ((IN+) - (IN−)) 0V to 1V LVDS Output Voltage (OUT+, OUT−) −0.3V to +4V LVDS Differential Output Voltage ((OUT+) - (OUT−)) 0V to 1V LVDS Output Short Circuit Current 5 ms Duration Junction Temperature +150°C Storage Temperature Range −65°C to +150°C Lead Temperature Range Soldering (4 sec.) +260°C Maximum Package Power Dissipation at 25°C SDA Package 2.08W Derate SDA Package 16.7 mW/°C above +25°C Package Thermal Resistance  θJA  θJC ESD Susceptibility HBM (Note 1) MM (Note 2) CDM (Note 3) Note 1: Human Body Model, applicable std. JESD22-A114C Note 2: Machine Model, applicable std. JESD22-A115-A Note 3: Field Induced Charge Device Model, applicable std. JESD22-C101-C +60.0°C/W +12.3°C/W ≥7 kV ≥250V ≥1250V Recommended Operating Conditions Supply Voltage (VCC) Receiver Differential Input Voltage (VID) Operating Free Air Temperature (TA) Min 3.0 0 −40 Typ 3.3 Max 3.6 1 +85 Units V V °C +25 DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7) Symbol VOD ΔVOD VOS ΔVOS IOS COUT ROUT Parameter Differential Output Voltage Change in Magnitude of VOD for Complimentary Output States Offset Voltage Change in Magnitude of VOS for Complimentary Output States Output Short Circuit Current (Note 8) Output Capacitance Output Termination Resistor RL = 100Ω OUT to GND OUT to VCC Any LVDS Output Pin to GND Between OUT+ and OUTRL = 100Ω Conditions Min 250 -35 1.05 -35 -25 7.5 1.2 100 1.2 Typ 350 Max 450 35 1.375 35 -50 50 Units mV mV V mV mA mA pF Ω LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-) 3 www.national.com DS25BR150 Symbol VID VTH VTL VCMR Parameter Input Differential Voltage Differential Input High Threshold Differential Input Low Threshold Common Mode Voltage Range Conditions Min 0 Typ Max 1 Units V mV mV V μA pF Ω LVDS INPUT DC SPECIFICATIONS (IN+, IN-) VCM = +0.05V or VCC-0.05V −100 VID = 100 mV VIN = 3.6V or 0V VCC = 3.6V or 0V Any LVDS Input Pin to GND Between IN+ and IN0.05 ±1 1.7 100 27 35 0 0 VCC 0.05 ±10 +100 IIN CIN RIN ICC Input Current Input Capacitance Input Termination Resistor Supply Current SUPPLY CURRENT mA Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. www.national.com 4 DS25BR150 AC Electrical Characteristics Symbol tPHLD tPLHD tSKD1 tSKD2 tLHT tHLT tDJ1 tDJ2 tRJ1 tRJ2 tTJ1 tTJ2 Parameter (Note 11) Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10) Conditions Min Typ 370 355 15 45 RL = 100Ω 80 80 2.5 Gbps 3.125 Gbps 1.25 GHz 1.5625 GHz 2.5 Gbps 3.125 Gbps 11 15 0.5 0.5 0.04 0.07 Max 520 520 100 160 150 150 33 41 1 1 0.11 0.15 Units ps ps ps ps ps ps ps ps ps ps UIP-P UIP-P LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-) Differential Propagation Delay High to Low Differential Propagation Delay Low to High Pulse Skew |tPLHD − tPHLD| (Note 12) Part to Part Skew (Note 13) Rise Time Fall Time RL = 100Ω JITTER PERFORMANCE (Figure 5) Deterministic Jitter (Peak-to-Peak Value ) (Note 15) Random Jitter (RMS Value) (Note 14) Total Jitter (Peak to Peak Value) (Note 16) VID = 350 mV VCM = 1.2V K28.5 (NRZ) VID = 350 mV VCM = 1.2V Clock (RZ) VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 11: Specification is guaranteed by characterization and is not tested in production. Note 12: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 13: tSKD2, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. Note 14: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically. Note 15: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted algebraically. Note 16: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted. 5 www.national.com DS25BR150 DC Test Circuits 30005520 FIGURE 1. Differential Driver DC Test Circuit AC Test Circuits and Timing Diagrams 30005521 FIGURE 2. Differential Driver AC Test Circuit 30005522 FIGURE 3. Propagation Delay Timing Diagram 30005523 FIGURE 4. LVDS Output Transition Times www.national.com 6 DS25BR150 30005529 FIGURE 5. Jitter Measurements Test Circuit 7 www.national.com DS25BR150 Device Operation INPUT INTERFACING The DS25BR150 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the DS25BR150 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS25BR150 inputs are internally terminated with a 100Ω resistor. 30005511 Typical LVDS Driver DC-Coupled Interface to DS25BR150 Input 30005512 Typical CML Driver DC-Coupled Interface to DS25BR150 Input 30005513 Typical LVPECL Driver DC-Coupled Interface to DS25BR150 Input www.national.com 8 DS25BR150 OUTPUT INTERFACING The DS25BR150 outputs signals are compliant to the LVDS standard. It can be DC-coupled to most common differential receivers. The following figure illustrates typ