3.125 Gbps LVDS Buffer

DS25BR100 3.125 Gbps LVDS Buffer with PE and EQ April 2007 DS25BR100 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization General Description The DS25BR100 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The DS25BR100 features transmit pre-emphasis (PE) and receive equalization (EQ), making it ideal for use as a repeater device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR110 features four levels of equalization for use as an optimized receiver device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization. Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce component count, and further minimize board space. Features ■ DC - 3.125 Gbps low jitter, high noise immunity, low power operation ■ Receive equalization reduces ISI jitter due to media loss ■ Transmit pre-emphasis drives lossy backplanes and cables ■ On-chip 100Ω input and output termination minimizes insertion and return losses, reduces component count and minimizes board space ■ 7 kV ESD on LVDS I/O pins protects adjoining components ■ Small 3 mm x 3 mm 8-LLP space saving package Applications ■ Clock and data buffering ■ Metallic cable driving and equalization ■ FR-4 equalization Typical Application 20179110 © 2007 National Semiconductor Corporation 201791 www.national.com DS25BR100 Block Diagram 20179101 Pin Diagram 20179104 Pin Descriptions Pin Name EQ IN+ INPE NC OUTOUT+ VCC GND Pin Name 1 2 3 4 5 6 7 8 DAP Pin Type Input Input Input Input NA Output Output Power Power Pin Description Equalizer select pin. Non-inverting LVDS input pin. Inverting LVDS input pin. Pre-emphasis select pin. "NO CONNECT" pin. Inverting LVDS output pin. Non-inverting LVDS Output pin. Power supply pin. Ground pad (DAP - die attach pad). Control Pins (PE and EQ) Truth Table EQ 0 0 1 1 PE 0 1 0 1 Equalization Level Low (Approx. 4 dB at 1.56 GHz) Low (Approx. 4 dB at 1.56 GHz) Medium (Approx. 8 dB at 1.56 GHz) Medium (Approx. 8 dB at 1.56 GHz) Pre-emphasis Level Off Medium (Approx. 6 dB at 1.56 GHz) Off Medium (Approx. 6 dB at 1.56 GHz) Ordering Codes and Configurations NSID DS25BR100TSD DS25BR110TSD DS25BR120TSD DS25BR150TSD Function Buffer/Repeater Receiver Driver Buffer/Repeater Available Equalization Levels Low / Medium Off / Low / Medium / High NA NA Available Pre-emphasis Levels Off / Medium NA Off / Low / Medium / High NA www.national.com 2 DS25BR100 Absolute Maximum Ratings (Note 4) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +4V LVCMOS Input Voltage (EQ, PE) −0.3V to (VCC + 0.3V) LVDS Input Voltage (IN+, IN−) −0.3V to +4V LVDS Differential Input Voltage ((IN+) - (IN−)) 0V to 1V LVDS Output Voltage (OUT+, OUT−) −0.3V to +4V LVDS Differential Output Voltage ((OUT+) - (OUT−)) 0V to 1V LVDS Output Short Circuit Current 5 ms Duration Junction Temperature +150°C Storage Temperature Range −65°C to +150°C Lead Temperature Range Soldering (4 sec.) +260°C Maximum Package Power Dissipation at 25°C SDA Package 2.08W Derate SDA Package 16.7 mW/°C above +25°C Package Thermal Resistance  θJA  θJC ESD Susceptibility HBM (Note 1) MM (Note 2) CDM (Note 3) Note 1: Human Body Model, applicable std. JESD22-A114C Note 2: Machine Model, applicable std. JESD22-A115-A Note 3: Field Induced Charge Device Model, applicable std. JESD22-C101-C +60.0°C/W +12.3°C/W ≥7 kV ≥250V ≥1250V Recommended Operating Conditions Supply Voltage (VCC) Receiver Differential Input Voltage (VID) Operating Free Air Temperature (TA) Min 3.0 Typ 3.3 Max 3.6 1.0 +85 Units V V °C −40 +25 DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7) Symbol VIH VIL IIH IIL VCL VOD ΔVOD VOS ΔVOS IOS COUT ROUT Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Clamp Voltage Differential Output Voltage Change in Magnitude of VOD for Complimentary Output States Offset Voltage Change in Magnitude of VOS for Complimentary Output States Output Short Circuit Current (Note 8) Output Capacitance Output Termination Resistor RL = 100Ω OUT to GND, PE = 0 OUT to VCC, PE = 0 Any LVDS Output Pin to GND Between OUT+ and OUTRL = 100Ω VIN = 3.6V VCC = 3.6V VIN = GND VCC = 3.6V ICL = −18 mA, VCC = 0V 250 -35 1.05 -35 -35 7 1.2 100 1.2 Conditions Min 2.0 GND 0 0 -0.9 350 Typ Max VCC 0.8 ±10 ±10 −1.5 450 35 1.375 35 -55 55 Units V V μA μA V mV mV V mV mA mA pF Ω LVCMOS INPUT DC SPECIFICATIONS (EQ, PE) LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-) 3 www.national.com DS25BR100 Symbol VID VTH VTL VCMR Parameter Input Differential Voltage Differential Input High Threshold Differential Input Low Threshold Common Mode Voltage Range Conditions Min 0 Typ Max 1 Units V mV mV V μA pF Ω LVDS INPUT DC SPECIFICATIONS (IN+, IN-) VCM = +0.05V or VCC-0.05V −100 VID = 100 mV VIN = GND or 3.6V VCC = 3.6V or 0.0V Any LVDS Input Pin to GND Between IN+ and INEQ = 0, PE = 0 0.05 ±1 1.7 100 35 43 0 0 VCC 0.05 ±10 +100 IIN CIN RIN ICC Input Current Input Capacitance Input Termination Resistor Supply Current SUPPLY CURRENT mA Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. www.national.com 4 DS25BR100 AC Electrical Characteristics Symbol tPHLD tPLHD tSKD1 tSKD2 tLHT tHLT tRJ1A tRJ2A Parameter (Note 11) Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10) Conditions Min Typ 350 350 45 45 RL = 100Ω 80 80 2.5 Gbps 3.125 Gbps 2.5 Gbps 3.125 Gbps 2.5 Gbps 3.125 Gbps 0.5 0.5 1 11 0.03 0.06 Max 465 465 100 150 150 150 1 1 16 31 0.09 0.14 Units ps ps ps ps ps ps ps ps ps ps UIP-P UIP-P LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-) Differential Propagation Delay High to Low Differential Propagation Delay Low to High Pulse Skew |tPLHD − tPHLD| (Note 12) Part to Part Skew (Note 13) Rise Time Fall Time RL = 100Ω JITTER PERFORMANCE WITH PE = OFF AND EQ = LOW (Figures 6, 7) Random Jitter (RMS Value) Input Test Channel D (Note 14) Deterministic Jitter (Peak to Peak) Input Test Channel D (Note 15) Total Jitter (Peak to Peak) Input Test Channel D (Note 16) VID = 350 mV VCM = 1.2V Clock (RZ) PE = 0, EQ = 0 VID = 350 mV VCM = 1.2V K28.5 (NRZ) PE = 0, EQ = 0 VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) PE = 0, EQ = 0 VID = 350 mV VCM = 1.2V Clock (RZ) PE = 0, EQ = 1 VID = 350 mV VCM = 1.2V K28.5 (NRZ) PE = 0, EQ = 1 VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) PE = 0, EQ = 1 VID = 350 mV VCM = 1.2V Clock (RZ) PE = 1, EQ = 0 VID = 350 mV VCM = 1.2V K28.5 (NRZ) PE = 1, EQ = 0 VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) PE = 1, EQ = 0 tDJ1A tDJ2A tTJ1A tTJ2A JITTER PERFORMANCE WITH PE = OFF AND EQ = MEDIUM (Figures 6, 7) tRJ1B tRJ2B Random Jitter (RMS Value) Input Test Channel E (Note 14) Deterministic Jitter (Peak to Peak) Input Test Channel E (Note 15) Total Jitter (Peak to Peak) Input Test Channel E (Note 16) 2.5 Gbps 3.125 Gbps 2.5 Gbps 3.125 Gbps 2.5 Gbps 3.125 Gbps 0.5 0.5 10 27 0.07 0.12 1 1 29 43 0.12 0.17 ps ps ps ps UIP-P UIP-P tDJ1B tDJ2B tTJ1B tTJ2B JITTER PERFORMANCE WITH PE = MEDIUM AND EQ = LOW (Figures 5, 7) tRJ1C tRJ2C Random Jitter (RMS Value) Input Test Channel D Output Test Channel B (Note 14) Deterministic Jitter (Peak to Peak) Input Test Channel D Output Test Channel B (Note 15) Total Jitter (Peak to Peak) Input Test Channel D Output Test Channel B (Note 16) 2.5 Gbps 3.125 Gbps 2.5 Gbps 3.125 Gbps 2.5 Gbps 3.125 Gbps 0.5 0.5 29 29 0.10 0.13 1 1 57 51 0.19 0.22 ps ps ps ps UIP-P UIP-P tDJ1C tDJ2C tTJ1C tTJ2C 5 www.national.com DS25BR100 Symbol tRJ1D tRJ2D Parameter Random Jitter (RMS Value) Input Test Channel E Output Test Channel B (Note 14) Deterministic Jitter (Peak to Peak) Input Test Channel E Output Test Channel B (Note 15) Total Jitter (Peak to Peak) Input Test Channel E Output Test Channel B (Note 16) Conditi