1.0 Gbps LVDS Buffer / Repeater

DS10BR150 1.0 Gbps LVDS Buffer / Repeater April 2007 DS10BR150 1.0 Gbps LVDS Buffer / Repeater General Description The DS10BR150 is a single channel 1.0 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce component count and further minimize board space. Features ■ DC - 1.0 Gbps low jitter, high noise immunity, low power operation ■ On-chip 100Ω input and output termination minimizes insertion and return losses, reduces component count and minimizes board space ■ 7 kV ESD on LVDS I/O pins protects adjoining components ■ Small 3 mm x 3 mm 8-LLP space saving package Applications ■ ■ ■ ■ Clock and data buffering OC-12 / STM-4 Fibre Channel (1GFC) FireWire 800 Typical Application 30001710 © 2007 National Semiconductor Corporation 300017 www.national.com DS10BR150 Block Diagram 30001701 Pin Diagram 30001702 Pin Descriptions Pin Name NC IN+ INNC NC OUTOUT+ VCC GND Pin Name 1 2 3 4 5 6 7 8 DAP Pin Type NA Input Input NA NA Output Output Power Power Pin Description "NO CONNECT" pin. Non-inverting LVDS input pin. Inverting LVDS input pin. "NO CONNECT" pin. "NO CONNECT" pin. Inverting LVDS output pin. Non-inverting LVDS Output pin. Power supply pin. Ground pad (DAP - die attach pad) Ordering Code NSID DS10BR150TSD Function Buffer / Repeater www.national.com 2 DS10BR150 Absolute Maximum Ratings (Note 4) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +4V LVDS Input Voltage (IN+, IN−) −0.3V to +4V LVDS Differential Input Voltage ((IN+) - (IN−)) 0V to 1V LVDS Output Voltage (OUT+, OUT−) −0.3V to +4V LVDS Differential Output Voltage ((OUT+) - (OUT−)) 0V to 1V LVDS Output Short Circuit Current 5 ms Duration Junction Temperature +150°C Storage Temperature Range −65°C to +150°C Lead Temperature Range Soldering (4 sec.) +260°C Maximum Package Power Dissipation at 25°C SDA Package 2.08W Derate SDA Package 16.7 mW/°C above +25°C Package Thermal Resistance  θJA  θJC ESD Susceptibility HBM MM CDM Note 1: Human Body Model, applicable std. JESD22-A114C Note 2: Machine Model, applicable std. JESD22-A115-A Note 3: Field Induced Charge Device Model, applicable std. JESD22-C101-C +60.0°C/W +12.3°C/W ≥7 kV ≥250V ≥1250V Recommended Operating Conditions Supply Voltage (VCC) Receiver Differential Input Voltage (VID) Operating Free Air Temperature (TA) Min 3.0 0 −40 Typ 3.3 Max 3.6 1 +85 Units V V °C +25 DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7) Symbol VOD ΔVOD VOS ΔVOS IOS COUT ROUT VID VTH VTL VCMR Parameter Differential Output Voltage Change in Magnitude of VOD for Complimentary Output States Offset Voltage Change in Magnitude of VOS for Complimentary Output States Output Short Circuit Current (Note 8) Output Capacitance Output Termination Resistor Input Differential Voltage Differential Input High Threshold Differential Input Low Threshold Common Mode Voltage Range VID = 100 mV VIN = 3.6V or 0V VCC = 3.6V or 0V Between IN+ and IN- Pins VCM = +0.05V or VCC-0.05V −100 0.05 ±1 1.7 100 16 21 RL = 100Ω OUT to GND OUT to VCC Any LVDS Output Pin to GND Between OUT+ and OUT- Pins 0 0 0 VCC 0.05 ±10 RL = 100Ω Conditions Min 250 -35 1.05 -35 -30 7.5 1.2 100 1 +100 1.2 Typ 350 Max 450 35 1.375 35 -50 50 Units mV mV V mV mA mA pF Ω V mV mV V μA pF Ω mA LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-) LVDS INPUT DC SPECIFICATIONS (IN+, IN-) IIN CIN RIN ICCD Input Current Input Capacitance Input Termination Resistor Total Supply Current SUPPLY CURRENT 3 www.national.com DS10BR150 AC Electrical Characteristics Symbol tPHLD2 tPLHD2 tSKD1 tSKD2 tLHT tHLT tDJ Parameter (Note 9) Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 7) Conditions Min Typ 380 410 30 45 RL = 100Ω 165 155 622 Mbps 1.06 Gbps 311 MHz 503 MHz 622 Mbps 1.06 Gbps 12 15 0.6 0.6 0.02 0.02 Max 600 600 150 160 400 400 39 42 1.3 1.1 0.04 0.05 Units ps ps ps ps ps ps ps ps ps ps UIP-P UIP-P LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-) Differential Propagation Delay High to Low Differential Propagation Delay Low to High Pulse Skew |tPLHD − tPHLD| (Note 10) Part to Part Skew (Note 11) Rise Time Fall Time Deterministic Jitter (Peak-to-Peak Value ) (Note 13) Random Jitter (RMS Value) (Note 12) Total Jitter (Peak to Peak Value) (Note 14) RL = 100Ω JITTER PERFORMANCE (Figure 5) VID = 350 mV VCM = 1.2V K28.5 (NRZ) VID = 350 mV VCM = 1.2V Clock (NRZ) VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) tRJ tTJ Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Note 9: Specification is guaranteed by characterization and is not tested in production. Note 10: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 11: tSKD2, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. Note 12: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically. Note 13: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted algebraically. Note 14: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted. www.national.com 4 DS10BR150 DC Test Circuits 30001720 FIGURE 1. Differential Driver DC Test Circuit AC Test Circuits and Timing Diagrams 30001721 FIGURE 2. Differential Driver AC Test Circuit 30001722 FIGURE 3. Propagation Delay Timing Diagram 30001723 FIGURE 4. LVDS Output Transition Times 5 www.national.com DS10BR150 30001729 FIGURE 5. Jitter Measurements Test Circuit www.national.com 6 DS10BR150 Device Operation INPUT INTERFACING The DS10BR150 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the DS10BR150 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS10BR150 inputs are internally terminated with a 100Ω resistor. 30001711 Typical LVDS Driver DC-Coupled Interface to DS10BR150 Input 30001712 Typical CML Driver DC-Coupled Interface to DS10BR150 Input 30001713 Typical LVPECL Driver DC-Coupled Interface to DS10BR150 Input 7 www.national.com DS10BR150 OUTPUT INTERFACING The DS10BR150 outputs signals are compliant to the LVDS standard. It can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a common mode input range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation. 30001714 Typical DS10BR150 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver www.national.com 8 DS10BR150 Typical Performance 30001730 30001731 A 622 Mbps NRZ PRBS-7 Output Eye Diagram V:100 mV / DIV, H:200 ps / DIV A 1062.5 Mbps NRZ PRBS-7 Output Eye Diagram V:100 mV / DIV, H:150 ps / DIV 30001732 Total Jitter as a Function of Input Amplitude 30001733 Total Jitter as a Function of Input Amplitude 9 www.national.com DS10BR150 Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS10BR150TSD NS Package Number SDA08A (See AN-1187 for PCB Design and Assembly Recommendations) www.national.com 10 DS10BR150 Notes 11 www.national.com DS10BR150 1.0 Gbps LVDS Buffer / Repeater Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL