Dual High-Speed MOS Driver

www.DataSheet4U.com DS0026 Dual High-Speed MOS Driver October 2000 DS0026 Dual High-Speed MOS Driver General Description DS0026 is a low cost monolithic high speed two phase MOS clock driver and interface circuit. Unique circuit design provides both very high speed operation and the ability to drive large capacitive loads. The device accepts standard TTL outputs and converts them to MOS logic levels. The device may be driven from standard 54/74 series and 54S/74S series gates and flip-flops or from drivers such as the DS8830 or DM7440. The DS0026 is intended for applications in which the output pulse width is logically controlled; i.e., the output pulse width is equal to the input pulse width. The DS0026 is designed to fulfill a wide variety of MOS interface requirements. Information on the correct usage of the DS0026 in these as well as other systems is included in the application note AN-76. Features n n n n n Fast rise and fall times — 20 ns 1000 pF load High output swing — 20V High output current drive — ±1.5 amps TTL compatible inputs High rep rate — 5 to 10 MHz depending on power dissipation n Low power consumption in MOS “0” state — 2 mW n Drives to 0.4V of GND for RAM address drive Connection Diagram (Top View) Dual-In-Line Package DS005853-2 Order Number DS0026CN See NS Package Number N08E © 2000 National Semiconductor Corporation DS005853 www.national.com DS0026 www.DataSheet4U.com Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. (V+) − (V−) Differential Voltage Input Current Input Voltage (VIN) − (V−) Peak Output Current Storage Temperature Range Lead Temperature (Soldering, 10 sec.) 22V 100 mA 5.5V 1.5A −65˚C to +150˚C 300˚C Operating Ratings (V+) − (V−) Differential Voltage Maximum Power Dissipation at TA = 25˚C (Note 7) N08E θJA N08E θJC Operating Temperature Range, TA 10V to 20V 1168mW 107˚C/W 37˚C/W 0˚C to +70˚C Electrical Characteristics (Notes 2, 3, 4) Symbol VIH IIH VIL IIL VOL VOH ICC(ON) ICC(OFF) Parameter Logic “1” Input Voltage Logic “1” Input Current Logic “0” Input Voltage Logic “0” Input Current Logic “1” Output Voltage Logic “0” Output Voltage “ON” Supply Current (one side on) “OFF” Supply Current V = 0V VIN − V− = 2.4V V− = 0V VIN − V = 0V VIN − V− = 2.4V, IOL = 1 mA VIN − V− = 0.4V, VSS ≥ V+ + 1.0V IOH = − 1 mA V − V = 20V, VIN − V = 2.4V V+ − V− = 20V, VIN − V− = 0V + − − − − Conditions Min 2 Typ 1.5 10 0.6 −3 V−+0.7 Max 15 0.4 −10 V−+1.0 Units V mA V µA V V V+ − 1.0 V+−0.8 30 10 40 100 mA µA Switching Characteristics (TA = 25˚C) (Notes 5, 6) Symbol tON tOFF tr Parameter Turn-On Delay Turn-Off Delay Rise Time Conditions Min 5 Typ 7.5 11 12 13 CL = 500 pF CL = 1000 pF CL = 500 pF CL = 1000 pF CL = 500 pF CL = 1000 pF CL = 500 pF CL = 1000 pF 15 20 30 36 12 17 28 31 18 35 40 50 16 25 35 40 15 Max 12 Units ns ns ns ns ns ns ns ns ns ns ns ns (Figure 1) (Figure 2) (Figure 1) (Figure 2) (Figure 1), (Note 5) (Figure 2), (Note 5) tf Fall Time (Figure 1), (Note 5) (Figure 2), (Note 5) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics provides conditions for actual device operation. Note 2: These specifications apply for V+ − V− = 10V to 20V, CL = 1000 pF, over the temperature range of 0˚C to +70˚C for the DS0026CN. Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis. Note 4: All typical values for TA = 25˚C. Note 5: Rise and fall time are given for MOS logic levels; i.e., rise time is transition from logic “0” to logic “1” which is voltage fall. Note 6: The high current transient (as high as 1.5A) through the resistance of the internal interconnecting V− lead during the output transition from the high state to the low state can appear as negative feedback to the input. If the external interconnecting lead from the driving circuit to V− is electrically long, or has significant dc resistance, it can subtract from the switching response. Note 7: Derate N08E package 9.3 mW/˚C for TA above 25˚C. www.national.com 2 www.DataSheet4U.com DS0026 Typical VBB Connection DS005853-8 Typical Performance Characteristics Input Current vs Input Voltage Supply Current vs Temperature Turn-On and Turn-Off Delay vs Temperature DS005853-23 DS005853-22 DS005853-24 Rise Time vs Load Capacitance Fall Time vs Load Capacitance DS005853-25 DS005853-26 3 www.national.com DS0026 www.DataSheet4U.com Typical Performance Characteristics Recommended Input Coding Capacitance (Continued) DC Power (PDC) vs Duty Cycle DS005853-28 DS005853-27 Schematic Diagram 1/2 DS0026 DS005853-10 www.national.com 4 www.DataSheet4U.com DS0026 AC Test Circuits and Switching Time Waveforms DS005853-13 DS005853-12 FIGURE 1. DS005853-15 DS005853-14 FIGURE 2. Typical Applications AC Coupled MOS Clock Driver Application Hints DRIVING THE MM5262 WITH THE DS0026 CLOCK DRIVER The clock signals for the MM5262 have three requirements which have the potential of generating problems for the user. These requirements, high speed, large voltage swing and large capacitive loads, combine to provide ample opportunity for inductive ringing on clock lines, coupling clock signals to other clocks and/or inputs and outputs and generating noise on the power supplies. All of these problems have the potential of causing the memory system to malfunction. Recognizing the source and potential of these problems early in the design of a memory system is the most critical step. The object here is to point out the source of these problems and give a quantitative feel for their magnitude. Line ringing comes from the fact that at a high enough frequency any line must be considered as a transmission line with distributed inductance and capacitance. To see how much ringing can be tolerated we must examine the clock voltage specification. Figure 3 shows the clock specification, in diagram form, with idealized ringing sketched in. The ringing of the clock about the VSS level is particularly critical. If the VSS − 1 VOH is not maintained, at all times, the information stored in the memory could be altered. Referring to Figure 1, if the threshold voltage of a transistor were −1.3V, the clock going to VSS − 1 would mean that all the devices, whose gates are tied to that clock, would be only 300 mV from turning on. The internal circuitry needs this noise margin and from the functional description of the RAM it is easy to see that turning a clock on at the wrong time can have disastrous results. 5 www.national.com DS005853-16 DC Coupled RAM Memory Address or Precharge Driver (Positive Supply Only) DS005853-17 DS0026 www.DataSheet4U.com Application Hints (Continued) DS005853-18 FIGURE 3. Clock Waveform Controlling the clock ringing is particularly difficult because of the relative magnitude of the allowable ringing, compared to magnitude of the transition. In this case it is 1V out of 20V or only 5%. Ringing can be controlled by damping the clock driver and minimizing the line inductance. Damping the clock driver by placing a resistance in series with its output is effective, but there is a limit since it also slows down the rise and fall time of the clock signal. Because the typical clock driver can be much faster than the worst case driver, the damping resistor serves the useful function of limiting the minimum rise and fall time. This is very important because the faster the rise and fall times, the worse the ringing problem becomes. The size of the damping resistor varies because it is dependent on the details of the actual application. It must be determined empirically. In practice a resistance of 10Ω to 20Ω is usually optimum. Limiting the inductance of the clock lines can be accomplished by minimizing their length and by laying out the lines such that the return current is closely coupled to the clock lines. When minimizing the length of clock lines it is important to minimize the distance from the clock driver output to the furthest point being driven. Because of this, memory boards are usually designed with clock drivers in the center of the memory array, rather than on one side, reducing the maximum distance by a factor of 2. Using multilayer printed circuit boards with clock lines sandwiched between the VDD and VSS power plains minimizes the inductance of the clock lines. It also serves the function of preventing the clocks from coupling noise into input and output lines. Unfortunately multilayer printed circuit boards are more expensive than two sided boards. The user must make the decision as to the necessity of multilayer boards. Suffice it to say here, that reliable memory boards can be designed using two sided printed circuit boards. DS005853-19 FIGURE 4. Clock Waveforms (Voltage and Current) Because of the amount of current that the clock driver must supply to its capacitive load, the distribution of power to the clock driver must be considered. Figure 4 gives the idealized voltage and current waveforms for a clock driver driving a 1000 pF capacitor with 20 ns rise and fall time. As can be seen the current is significant. This current flows in the VDD and VSS power lines. Any significant inductance in the lines will produce large voltage transients on the power supplies. A bypass capacitor, as close as possible to the clock driver, is helpful in minimizing this problem. This bypass is most effective when connected between