10/100Mbps Fast Ethernet Physical Layer Single Chip Transceiver

www.DataSheet4U.com DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver General Description The DM9131 is a physical-layer, single-chip, lowpower transceiver for 100BASE-TX and 10BASE-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Cable 5 (UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet, and it also provides PECL interface to connect the external fiber optical transceiver. Through the Media Independent Interface (MII), the DM9131 connects to the Medium Access Control (MAC) layer, ensuring a high interoperability among products from different vendors. The DM9131 uses a low-power and high-performance CMOS process. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE802.3u, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit (TPMAU). The DM9131 provides a strong support for the autonegotiation function utilizing automatic media speed and protocol selection. Furthermore, due to the builtin wave-shaping filter, the DM9131 needs no external filter to transport signals to the media in 100M or 10M Ethernet operation. Block Diagram 100Base-FX PECL Interface 100Base-TX Transceiver 100BaseTX PCS MII Interface 10Base-T TX/RX Module LED Driver Auto-Negotiation Clock Circuit Block Biasing/ Power Block MII Register MII Management Control Final Version: DM9131-DS-F01 April 7, 2000 1 www.DataSheet4U.com DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Table of Contents General Description ................................................1 DAVICOM Specified Interrupt Register - 21.......... 20 Block Diagram........................................................1 Features .................................................................3 Pin Configuration: DM9101E LQFP ........................4 Pin Description .......................................................5 Normal MII Interface, 21 pins...............................5 Media Interface, 5 pins ........................................6 LED Interface, 5 pins ...........................................6 Mode, 11 pins ......................................................7 Bias and Clock, 6 pins .........................................7 Power and Others, 52 pins...................................8 Functional Description Transmit Section .................................................9 100Base-TX Operation ........................................9 MII Serial Management Interface.........................9 Management Interface – Read Frame Structure ..9 Management Interface – Write Frame Structure .9 DAVICOM Specified Receive Error Counter Register (RECR) - 22 ......................................................... 20 DAVICOM Specified Disconnect Counter Register (DISCR) - 23 ........................................................ 20 Absolute Maximum Ratings.................................. 21 Operating Conditions......................................... 21 MII Register Description........................................10 - Key To Default ...................................................10 Basic Mode Control Register (BMCR) - 00............11 Basic Mode Status Register (BMSR) - 01 .............12 PHY ID Identifier Register #1 (PHYIDR1) - 02 ......13 PHY ID Identifier Register #2 (PHYIDR2) - 03 ......13 Auto-negotiation Advertisement Register (ANAR) - 04.......................................................................14 Auto-negotiation Link Partner Ability Register (ANLPAR) - 05......................................................15 Auto-negotiation Expansion Register (ANER) - 06.......................................................................16 DAVICOM Specified Configuration Register (DSCR) - 16.......................................................................16 DAVICOM Specified Configuration and Status Register (DSCSR) - 17 .........................................18 10Base-T Configuration / Status (10BTCSR) - 18 .19 2 T T T T T T T T T T T T T T T T T T T T T T T T T T T DC Electrical Characteristics ................................ 22 AC Electrical Characteristics & Timing Waveforms ............................................................................ 22 TP Interface ...................................................... 22 Oscillator/Crystal Timing ................................... 22 MDC/MDIO Timing............................................ 23 MDIO Timing when OUTPUT by STA ............... 23 MDIO Timing when OUTPUT by DM9131 ......... 23 MII 100Base-TX Transmit Timing Parameters... 24 MII 100Base-TX Transmit Timing Diagram........ 24 MII 100Base-TX Receive Timing Parameters.... 24 MII 100Base-TX Receive Timing Diagram......... 25 MII 10Base-T Nibble Transmit Timing Parameters ......................................................................... 25 MII 10Base-T Nibble Transmit Timing Diagram . 25 MII 10Base-T Receive Nibble Timing Parameters ......................................................................... 26 MII-10Base-T Receive Nibble Timing Diagram.. 26 Auto-negotiation and Fast Link Pulse Timing Parameters ....................................................... 26 Auto-negotiation and Fast Link Pulse Timing Diagram ............................................................ 27 Package Information ............................................ 28 Ordering Information ............................................ 29 Disclaimer ............................................................ 29 Company Overview.............................................. 29 Product ................................................................ 29 Warning ............................................................... 29 Contact Windows ................................................. 29 Final Version: DM9131-DS-F01 April 7, 2000 www.DataSheet4U.com DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Final Version: DM9131-DS-F01 April 7, 2000 3 www.DataSheet4U.com DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Features 4 T T T T T T T T Fully compliant with IEEE 802.3u 10Base-T/100BaseTX Compliant with ANSI X3T12 TP-PMD 1995 standard Support Auto-Negotiation function, compliant to IEEE 802.3u Single-chip fully integrated Physical layer interface directly to magnetic Integrated 10Base-T and 100Base-TX transceiver On-chip filtering, no need for external filters Selectable repeater or node mode Far end fault signaling option in FX mode Selectable twisted-pair or fiber mode output Selectable full-duplex or half-duplex operation MII management interface with maskable interrupts output capability Provides Loopback mode for easy system diagnostics Status LED output provides Link & Activity, Speed10/100 and Full-duplex/Collision LED Low-Power, Single-Supply 3.3V CMOS technology Compatible with 3.3V and 5.0V tolerant I/O 100-pin LQFP T T T T T T T T Final Version: DM9131-DS-F01 April 7, 2000 www.DataSheet4U.com DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Pin Configuration OSCIN/REF_CLK TESTMODE 77 PHYADR0 PHYADR1 PHYADR2 PHYADR3 PHYADR4 78 OSCSEL DGND DGND AGND DVCC AVCC XT1 XT2 NC NC NC NC NC NC NC NC 100 93 99 98 97 96 94 92 91 90 89 88 87 86 85 84 83 95 82 81 80 79 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC BGRESG BGRES NC AVCC AVCC RX+/FXRD+ RX-/FXRDAGND AGND AGND AGND TX+/FXTD+ TX-/FXTDNC AVCC PLLVCC NC PLLGND DGND NC OPMODE0 OPMODE1 OPMODE2 NC NC SD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 29 36 37 39 45 27 28 30 31 32 33 34 35 38 40 41 42 43 44 47 48 49 46 50 NC NC RESET# NC DVCC NC RXEN RXER/RXD[4]/RPTR RXDV COL CRS/BP4B5B RXCLK MDINTR# NC RXD[0] RXD[1] RXD[2] RXD[3] NC DVCC NC MDIO MDC NC NC DM9131 SPEEDLED# PWRDWN DVCC LINK&ACTLED# LINKLED DVCC FDX/COLLED# NC TXCLK DGND TXEN RMII DGND NC NC NC NC NC TXD[3] TXD[2] TXD[1] Final Version: DM9131-DS-F01 April 7, 2000 TXER/TXD[4] TRFLED# TXD[0] NC 5 www.DataSheet4U.com DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Pin Description I : Input, O : Output, LI : Latch input when power-up/reset, Z : Tri-State output Normal MII interface, 21 pins Pin No. Pin Name 38 TXER/TXD[4] 42,41,40,39 TXD[0:3] I/O Description I Transmit Error/The fifth TXD data bit In 100Mbps mode, when the signal actives high and TXEN actives, the HALT symbol is substituted for the actual data nibble. In 10Mbps, the input is ignored. In bypass mode (bypass BP4B5B), TXER becomes the TXD[4] pin, the fifth TXD data bit of the 5B symbol. I Transmit Data 4 bits nibble data input (synchronous to the TXCLK) when in 10/100Mbps nibble mode. In 10Mbps serial mode, the TXD[0] pin is used as the serial data input pin, and TXD[1:3] are ignored. I Transmit Enable Active high to indicate the presence of valid nibble data on the TXD[0:3] for both 100Mbps and 10Mbps nibble mode. In 10Mbps serial mode, active high indicates the presence of valid 10Mbps data on TXD[0]. Transmit Clock The transmitting clock provides the timing reference for the transfer of the TXEN, TXD, and TXER. TXCLK is provided by the PHY. 25MHz in 100Mbps nibble mode, 2.5MHz in 10Mbps nibble mode, 10MHz in 10Mbps serial mode. Management Data Clock Synchronous clock for the MDIO management data. This clock is provided by management entity, and it is up to 2.5MHZ Management Data I/O Bi-directional management data that may be provided by the station management entity or the PHY. Receive Data Output 4 bits nibble data output (synchronous to RXCLK) when in 10/100Mbps nibble mode. In 10Mbps serial mode, the RXD[0] pin is used as the serial data output pin, and the RXD[1:3] are ignored. Stat