Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops

DM54LS73A DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs June 1989 DM54LS73A DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse The data on the J and K inputs is allowed to change while the clock is high or low without affecting the outputs as long as setup and hold times are not violated A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs Connection Diagram Dual-In-Line Package www.DataSheet4U.com TL F 6372 – 1 Order Number DM54LS73AJ DM54LS73AW DM74LS73AM or DM74LS73AN See NS Package Number J14A M14A N14A or W14B Function Table Inputs CLR L H H H H H CLK X J X L H L H X K X L L H H X Q L Q0 H L Toggle Q0 Q0 Outputs Q H Q0 L H v v v v H H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level v e Negative going edge of pulse Q0 e The output logic level before the indicated input conditions were established Toggle e Each output changes to the complement of its previous level on each falling edge of the clock pulse C1995 National Semiconductor Corporation TL F 6372 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Input Voltage 7V 7V Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation Operating Free Air Temperature Range b 55 C to a 125 C DM54LS DM74LS 0 C to a 70 C b 65 C to a 150 C Storage Temperature Range Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK fCLK tW Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 2) Clock High Preset Low Clear Low tW Pulse Width (Note 3) Clock High Preset Low Clear Low tSU tSU tH tH TA Setup Time (Notes 1 and 2) Setup Time (Notes 1 and 3) Hold Time (Notes 1 and 2) Hold Time (Notes 1 and 3) Free Air Operating Temperature 0 0 20 25 25 25 30 30 20v 25v 0v 5v b 55 DM54LS73A Nom 5 Max 55 Min 4 75 2 07 b0 4 DM74LS73A Nom 5 Max 5 25 Units V V 08 b0 4 45 2 V mA mA MHz MHz 4 30 25 0 0 20 25 25 25 30 30 20v 25v 0v 5v 125 0 8 30 25 ns ns ns ns ns ns 70 C Note 1 The symbol (v) indicates the falling edge of the clock pulse is used for reference Note 2 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5V Note 3 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5V 2 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIL e Max VIH e Min IOL e 4 mA VCC e Min II Input Current Input Voltage Max VCC e Max VI e 7V DM54 DM74 DM54 DM74 DM74 JK Clear Clock IIH High Level Input Current VCC e Max VI e 2 7V JK Clear Clock IIL Low Level Input Current VCC e Max VI e 0 4V JK Clear Clock IOS Short Circuit Output Current Supply Current VCC e Max (Note 2) VCC e Max (Note 3) DM54 DM74 b 20 b 20 Min Typ (Note 1) Max b1 5 Units V V 25 27 34 34 0 25 0 35 0 25 04 05 04 01 03 04 20 60 80 b0 4 b0 8 b0 8 b 100 b 100 VOL V mA mA mA mA mA ICC 4 6 Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter From (Input) To (Output) RL e 2 kX CL e 15 pF Min fMAX tPHL tPLH tPLH tPHL Maximum Clock Frequency Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Clear to Q Clear to Q Clock to Q or Q Clock to Q or Q 30 20 20 20 20 Max CL e 50 pF Min 25 28 24 24 28 Max MHz ns ns ns ns Units Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second For devices with feedback from the outputs where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO e 2 25V and 2 125V for DM54 and DM74 series respectively with the minimum and maximum limits reduced by one half from their stated values This is very useful when using automatic test equipment Note 3 With all outputs open ICC is measured with the Q and Q outputs high in turn At the time of measurement the clock is grounded 3 Physical Dimensions inches (millimeters) 14-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS73AJ NS Package Number J14A 4 Physical Dimensions inches (millimeters) (Continued) 14-Lead Small Outline Molded Package (M) Order Number DM74LS73AM NS Package Number M14A 14-Lead Molded Dual-In-Line Package (N) Order Number DM74LS73AN NS Package Number N14A 5 DM54LS73A DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs Physical Dimensions inches (millimeters) (Continued) 14-Lead Ceramic Flat Package (W) Order Number DM54LS73AW NS Package Number W14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th 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