Integrated Digital Audio Interface Receiver and Transmitter

www.DataSheet4U.com Burr Brown Products from Texas Instruments DIX 419 2 DIX4192 SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Integrated Digital Audio Interface Receiver and Transmitter FEATURES • Digital Audio Interface Transmitter (DIT) – Supports Sampling Rates Up to 216kHz – Includes Differential Line Driver and CMOS Buffered Outputs – Block-Sized Data Buffers for Both Channel Status and User Data – Status Registers and Interrupt Generation for Flag and Error Conditions Digital Audio Interface Receiver (DIR) – PLL Lock Range Includes Sampling Rates from 20kHz to 216kHz – Includes Four Differential Input Line Receivers and an Input Multiplexer – Bypass Multiplexer Routes Line Receiver Outputs to Line Driver and Buffer Outputs – Block-Sized Data Buffers for Both Channel Status and User Data – Automatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937 formats) – Audio CD Q-Channel Sub-Code Decoding and Data Buffer – Status Registers and Interrupt Generation for Flag and Error Conditions – Low Jitter Recovered Clock Output User-Selectable Serial Host Interface: SPI™ or I2C™ – Provides Access to On-Chip Registers and Data Buffers • Two Audio Serial Ports (Ports A and B) – Synchronous Serial Interface to External Signal Processors, Data Converters, and Logic – Slave or Master Mode Operation with Sampling Rates up to 216kHz – Supports Left-Justified, Right-Justified, and Philips I2S™ Data Formats – Supports Audio Data Word Lengths Up to 24 Bits Four General-Purpose Digital Outputs – Multifunction Programmable Via Control Registers Extensive Power-Down Support – Functional Blocks May Be Disabled Individually When Not In Use Operates From +1.8V Core and +3.3V I/O Power Supplies Small TQFP-48 Package, Compatible with the SRC4382 and SRC4392 • • • • • APPLICATIONS • • • • • • • DIGITAL AUDIO RECORDERS AND MIXING DESKS DIGITAL AUDIO INTERFACES FOR COMPUTERS DIGITAL AUDIO ROUTERS AND DISTRIBUTION SYSTEMS BROADCAST STUDIO EQUIPMENT DVD/CD RECORDERS SURROUND SOUND DECODERS AND A/V RECEIVERS CAR AUDIO SYSTEMS • Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Dolby is a registered trademark of Dolby Laboratories, Inc. I2C, I2S are trademarks of Koninklijke Philips Electronics N.V. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 DESCRIPTION The DIX4192 is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The DIX4192 combines a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks. The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards. The audio serial ports and DIT may be operated at sampling rates up to 216kHz. The DIR lock range includes sampling rates from 20kHz to 216kHz. The DIX4192 is configured using on-chip control registers and data buffers, which are accessed through either a 4-wire serial peripheral interface (SPI) port, or a 2-wire Philips I2C bus interface. Status registers provide access to a variety of flag and error bits, which are derived from the various function blocks. An open-drain interrupt output pin is provided, and is supported by flexible interrupt reporting and mask options via control register settings. A master reset input pin is provided for initialization by a host processor or supervisory functions. The DIX4192 requires a +1.8V core logic supply, in addition to a +3.3V supply for powering portions of the DIR, DIT, and line driver and receiver functions. A separate logic I/O supply supports operation from +1.65V to +3.6V, providing compatibility with low voltage logic interfaces typically found on digital signal processors and programmable logic devices. The DIX4192 is available in a lead-free, TQFP-48 package, and is pin- and register-compatible with the Texas Instruments SRC4382 and SRC4392 products. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PACKAGE DESIGNATOR PFB SPECIFIED TEMPERATURE RANGE –40°C to +85°C PACKAGE MARKING DIX4192I ORDERING NUMBER DIX4192IPFBT DIX4192IPFBR TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2000 PRODUCT DIX4192 (1) PACKAGE TQFP-48 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Power supplies VDD18 VDD33 VIO VCC Digital input voltage: Digital logic RXCKI, CPM, CS, CCLK, CDIN, CDOUT, INT, RST, MCLK, BLS, SYNC, BCKA, BCKB, LRCKA, LRCKB, SDINA, SDINB Line receiver input voltage (per pin) RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4– Input current (all pins except power and ground) Ambient operating temperature Storage temperature (1) –0.3V to (VIO + 0.3V) –0.3V to +2.0V –0.3V to +4.0V –0.3V to +4.0V –0.3V to +4.0V (VDD33 + 0.3) VPP ±10mA –40°C to +85°C –65°C to +150°C These limits are stress ratings only. Stresses beyond these limits may result in permanent damage. Extended exposure to absolute maximum ratings may degrade device reliability. Normal operation or performance at or beyond these limits is not specified or ensured. 2 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS: General, DIR, and DIT All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. DIX4192 PARAMETER DIGITAL I/O CHARACTERISTICS (All I/O pins except line receivers and line driver) High-level input voltage, VIH Low-level input voltage, VIL High-level input current, IIH Low-level input current, VIL High-level output voltage, VOH Low-level output voltage, VOL Input capacitance, CIN LINE RECEIVER INPUTS (RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4–) Voltage across a given differential input pair 150 IO = –4mA IO = +4mA 0.8 × VIO 0 3 0.7 × VIO 0 0.5 0.5 VIO 0.3 × VIO 10 10 VIO 0.2 × VIO V V µA µA V V pF CONDITIONS MIN TYP MAX UNITS Differential input sensitivity, VTH Input hysteresis, VHY LINE DRIVER OUTPUTS (TX+, TX–) Differential output voltage, VTXO MASTER CLOCK INPUT Master clock input (MCLK) frequency, fMCLK Master clock input (MCLK) duty cycle, fMCLKD DIGITAL AUDIO INTERFACE RECEIVER (DIR) PLL lock range Reference clock input (RXCKI) frequency, fRXCKI Reference clock input (RXCKI) duty cycle, fRXCKID Recovered clock output (RXCKO) frequency, fRXCKO Recovered clock output (RXCKO) duty cycle, fRXCKOD Recovered clock output (RXCKO) intrinsic jitter DIGITAL AUDIO INTERFACE TRANSMITTER (DIT) Intrinsic output jitter 150 200 mV mV RL = 110Ω Across TX+ and TX– 5.4 VPP 27.7 55 MHz % 1 45 20 3.5 45 3.5 45 Measured cycle-to-cycle 250 216 27.7 55 27.7 55 kHz MHz % MHz % ps RMS Measured cycle-to-cycle 200 ps RMS Submit Documentation Feedback 3 DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS: Audio Serial Ports All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. DIX4192 PARAMETER AUDIO SERIAL PORTS (Port A and Port B) LRCK clock frequency, fLRCK LRCK clock duty cycle, tLRCKD BCK clock frequency, fBCK BCK high pulse width, tBCKH BCK low pulse width, tBCKL Audio data Input (SDIN) setup time, tAIS Audio data input (SDIN) hold time, tAISH Audio data output (SDOUT) delay, tADD 0 10 10 10 10 10 0 50 13.824 216 kHz % MHz ns ns ns ns ns CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS: SPI Interface All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. DIX4192 PARAMETER HOST INTERFACE: SPI Mode Serial clock (CCLK) frequency, fCCLK CS falling to CCLK rising, tCSCR CCLK falling to CS rising, tCFCS CDIN data setup time, tCDS CDIN data hold time, tCDH CCLK falling to CDOUT data valid, tCFDO CS rising to CDOUT high-impedance, tCSZ 0 8 7 7 6 3 3 40 MHz ns ns ns ns ns ns CONDITIONS MIN TYP MAX UNITS 4 Submit Documentation Feedback DIX4192 www.ti.com SBFS031C – JANUARY 2006 – REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS: I2C Standard and Fast Modes All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted. DIX4192 PARAMETER HOST INTERFACE: I2C Standard Mode (1) 0 4 4.7 4 4.7 0 (2) 250 1000 300 4 4.7 400 0.1 × VIO 0.2 × VIO 3.45 (3) 100 kHz µs µs µs µs µs ns ns ns µs µs pF V V CONDITIONS MIN TYP MAX UNITS SCL clock frequency, fSCL Hold time repeated START condition, tHDSTA Low period of SCL clock, tLOW High period of SCL clock, tHIGH Setup time repeated START condition, tSUSTA Data hold time, tHDDAT Data setup time, tSUDAT Rise time for Both SDA and SDL, tR Fall time for Both SDA and SDL, tF Setup time for STOP condition, tSUSTO Bus free time betwe