24-Bit Digital Audio Interface Receiver

www.DataSheet4U.com Burr Brown Products from Texas Instruments DIR9001 SLES198 – DECEMBER 2006 96-kHz, 24-Bit Digital Audio Interface Receiver FEATURES • One-Chip Digital Audio Interface Receiver (DIR) Including Low-Jitter Clock-Recovery System Compliant With Digital Audio Interface Standards: IEC60958 (former IEC958), JEITA CPR-1205 (former EIAJ CP-1201, CP-340), AES3, EBU tech3250 Clock Recovery and Data Decode From Biphase Input Signal, Generally Called S/PDIF, EIAJ CP-1201, IEC60958, AES/EBU Biphase Input Signal Sampling Frequency (fS) Range: 28 kHz to 108 kHz Low-Jitter Recovered System Clock: 50 ps Jitter Tolerance Compliant With IEC60958-3 Selectable Recovered System Clock: 128 fS, 256 fS, 384 fS, 512 fS Serial Audio Data Output Formats: 24-Bit I2S; MSB-First, 24-Bit Left-Justified; MSB-First 16-, 24-Bit Right-Justified User Data, Channel-Status Data Outputs Synchronized With Decoded Serial Audio Data No External Clock Required for Decode Includes Actual Sampling Frequency Calculator (Needs External 24.576-MHz Clock) Function Control: Parallel (Hardware) Functions Similar and Pin Assignments Equivalent to Those of DIR1703 Single Power Supply: 3.3 V (2.7 V to 3.6 V) Wide Operating Temperature Range: –40°C to 85°C 5 V-Tolerant Digital Inputs Package: 28-pin TSSOP, Pin Pitch: 0,65 mm APPLICATIONS • • • • • • • • AV/DVD Receiver, AV Amplifier Car or Mobile Audio System Digital Television Musical Instruments Recording Systems High-End Audio/Sound Card for PC Replacement of DIR1703 Other Applications Requiring S/PDIF Receiver • • • • • • • DESCRIPTION The DIR9001 is a digital audio interface receiver that can receive a 28-kHz to 108-kHz samplingfrequency, 24-bit-data-word, biphase-encoded signal. The DIR9001 complies with IEC60958-3, JEITA CPR-1205 (Revised version of EIAJ CP-1201), AES3, EBUtech3250, and it can be used in various applications that require a digital audio interface. The DIR9001 supports many output system clock and output data formats and can be used flexibly in many application systems. As the all functions which the DIR9001 provides can be controlled directly through control pins, it can be used easily in an application system that does not have a microcontroller. Also, as dedicated pins are provided for the channel-status bit and user-data bit, processing of their information can be easily accomplished by connecting with a microcontroller, DSP, etc. The DIR9001 does not require an external clock source or resonator for decode operation if the internal actual-sampling-frequency calculator is not used. Therefore, it is possible to reduce the cost of a system. The operating temperature range of the DIR9001 is specified as –40°C to 85°C, which makes it suitable for automotive applications. • • • • • • • • • Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SpAct is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated DIR9001 SLES198 – DECEMBER 2006 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VCC VDD VCC to VDD AGND to DGND (1) VALUE Supply voltage Supply voltage differences Ground voltage differences Digital input voltage Analog input voltage Digital input Digital output XTI, XTO FILT –0.3 to 4 ±0.1 ±0.1 –0.3 to 6.5 –0.3 to (VDD + 0.3) < 4 –0.3 to (VCC + 0.3) < 4 –0.3 to (VCC + 0.3) < 4 ±10 –40 to 125 –55 to 150 150 260 260 UNIT V V V V V mA °C °C °C °C, 5 s °C Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) Package temperature (reflow, peak) (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VCC VDD Analog supply voltage Digital supply voltage Digital input clock frequency XTI is connected to clock source XTI is connected to DGND 2.7 2.7 NOM 3.3 3.3 24.576 Not required 20 10 –40 85 MAX 3.6 3.6 UNIT VDC VDC MHz MHz pF pF °C Digital output load capacitance, except SCKO Digital output load capacitance (SCKO) TA Operating free-air temperature 2 Submit Documentation Feedback www.ti.com DIR9001 SLES198 – DECEMBER 2006 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VDD = VCC = 3.3 V (unless otherwise noted) PARAMETER DIGITAL INPUT/OUTPUT CHARACTERISTICS VIH VIL VIH VIL VOH VOL IIH IIL IIH IIL IIH IIL Input logic level (1) Input logic level (2) Output logic level (3) Input leakage current (4) Input leakage current (5) Input leakage current (6) IO = 4 mA IO = –4 mA VIN = VDD VIN = 0 V VIN = VDD VIN = 0 V VIN = VDD VIN = 0 V –10 –10 –100 –10 –10 28 IEC60958-3 (2003-01) From biphase signal detection to error-out release (ERROR = L) 16 128 fS SCKO frequency 256 fS 384 fS 512 fS BCKO frequency LRCKO frequency SCKO jitter SCKO duty cycle XTI SOURCE CLOCK XTI is connected to clock source XTI source clock frequency Frequency accuracy XTI input-clock duty cycle POWER SUPPLY AND SUPPLY CURRENT VCC VDD (1) (2) (3) (4) (5) (6) Operation voltage range 2.7 2.7 3.3 3.3 3.6 3.6 VDC XTI is connected to DGND XTI is connected to clock source XTI is connected to clock source –100 45% 24.576 Not required 100 55% MHz ppm 64 fS fS fS = 48 kHz, SCKO = 256 fS, measured periodic 45% 3.584 7.168 10.752 14.336 1.792 28 50 Compliant 100 ms –65 10 10 108 65 0.7 VDD 2 0.85 VDD 0.15 VDD 100 10 10 VDD 0.3 VDD 5.5 0.8 VDC VDC VDC µA µA µA TEST CONDITIONS MIN TYP MAX UNIT BIPHASE SIGNAL INPUT AND PLL Input sampling frequency range Jitter tolerance — (IEC60958-3) PLL lock-up time RECOVERED CLOCK AND DATA Serial audio data width 24 13.824 27.648 41.472 55.296 6.912 108 100 55% MHz kHz ps rms MHz Bit kHz CMOS compatible input: XTI (not 5-V tolerant) 5-V tolerant TTL inputs: RXIN, FMT0, FMT1, PSCK0, PSCK1, CKSEL, RST, RSV CMOS outputs: XTO, SCKO, BCKO, LRCKO, DOUT, UOUT, COUT, BFRAME, ERROR, CLKST, AUDIO, EMPH, FSOUT0, FSOUT1 Internal pulldowns: FMT0, FMT1, PSCK0, PSCK1, CKSEL, RSV Internal pullup: RST No internal pullup and pulldown: RXIN, XTI Submit Documentation Feedback 3 DIR9001 SLES198 – DECEMBER 2006 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VCC = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS fS = 96 kHz, PLL locked, XTI connected to DGND ICC Supply current (7) fS = 96 kHz, PLL locked, XTI connected to 24.576-MHz resonator RXIN = H or L, XTI = L, RST = L fS = 96 kHz, PLL locked, XTI connected to DGND IDD Supply current (7) fS = 96 kHz, PLL locked, XTI connected to 24.576-MHz resonator RXIN = H or L, XTI = L, RST = L fS = 96 kHz, PLL locked, XTI connected to DGND PD Power dissipation (7) fS = 96 kHz, PLL locked, XTI connected to 24.576-MHz resonator RXIN = H or L, XTI = L, RST = L TEMPERATURE RANGE TA θJA (7) Operation temperature range Thermal resistance 28-pin T-SSOP –40 105 85 °C °C/W MIN TYP 6 6 130 6 9 72 40 50 0.67 55 68 8.3 12.4 MAX 8.3 8.3 UNIT mA mA µA mA mA µA mW mW mW No load connected to SCKO, BCKO, LRCKO, DOUT, COUT, VOUT, BFRAME, FSOUT0, FSOUT1, CLKST, ERROR, EMPH, AUDIO PIN ASSIGNMENTS DIR9001 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AUDIO FSOUT0 FSOUT1 SCKO VDD DGND XTO XTI CLKST LRCKO BCKO DOUT PSCK0 PSCK1 CKSEL ERROR 28 27 FMT1 26 FMT0 25 VCC 24 AGND FILT RST RXIN RSV BFRAME EMPH UOUT COUT 23 22 21 20 19 18 17 16 15 4 Submit Documentation Feedback www.ti.com DIR9001 SLES198 – DECEMBER 2006 TERMINAL FUNCTIONS TERMINAL NAME AGND AUDIO BCKO BFRAME CKSEL CLKST COUT DGND DOUT EMPH ERROR FILT FMT0 FMT1 FSOUT0 FSOUT1 LRCKO PSCK0 PSCK1 RST RSV RXIN SCKO UOUT VCC VDD XTI XTO (1) (2) (3) NO. 23 1 11 18 28 9 15 6 12 17 27 22 25 26 2 3 10 13 14 21 19 20 4 16 24 5 8 7 I/O – OUT OUT OUT IN OUT OUT – OUT OUT OUT – IN IN OUT OUT OUT IN IN IN IN IN OUT OUT – – IN OUT CMOS Schmitt-trigger CMOS Pulldown Pulldown Pullup Pulldown 5-V tolerant TTL CMOS CMOS Pulldown Pulldown 5-V tolerant TTL 5-V tolerant TTL CMOS CMOS CMOS 5-V tolerant TTL 5-V tolerant TTL 5-V tolerant TTL CMOS CMOS CMOS Pulldown CMOS CMOS CMOS 5-V tolerant TTL CMOS CMOS PULL UP/DOWN REMARKS Analog ground Channel-status data information of non-audio sample word, active-low Audio data bit clock output Indication of top block of biphase input signal Selection of system clock source, Low: PLL (VCO) clock, High: XTI clock (1) Clock change/transition signal output Channel-status data serial output synchronized with LRCKO Digital ground 16-bit/24-bit decoded serial digital audio data output Channel-status data information of pre-emphasis (50 µs/15 µs) Indication of internal PLL or dat