Description
DAC124S085 12-Bit Micro Power QUAD Digital-to-Analog Converter with Rail-to-Rail Output January 2007 DAC124S085 12-Bit Micro Power QUAD Digital-to-Analog Converter with Rail-to-Rail Output General Description The DAC124S085 is a full-featured, general purpose QUAD 12-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7V to 5.5V supply and consumes 1.1 mW at 3V and 2.4 mW at 5V. The DAC124S085 is packaged in 10-lead LLP and MSOP packages. The 10-lead LLP package makes the DAC124S085 the smallest QUAD DAC in its class. The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 40 MHz over the entire supply voltage range. Competitive devices are limited to 25 MHz clock rates at supply voltages in the 2.7V to 3.6V range. The serial interface is compatible with standard SPI™, QSPI, MICROWIRE and DSP interfaces. The reference for the DAC124S085 serves all four channels and can vary in voltage between 1V and VA, providing the widest possible output dynamic range. The DAC124S085 has a 16-bit input shift register that controls the outputs to be updated, the mode of operation, the powerdown condition, and the binary input data. All four outputs can be updated simultaneously or individually depending on the setting of the two mode of operation bits. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three different termination options. The low power consumption and small packages of the DAC124S085 make it an excellent choice for use in battery operated equipment. The DAC124S085 is one of a family of pin compatible DACs, including the 8-bit DAC084S085 and the 10-bit DAC104S085. The DAC124S085 operates over the extended industrial temperature range of −40°C to +105°C. Features ■ ■ ■ ■ ■ ■ ■ ■ Guaranteed Monotonicity Low Power Operation Rail-to-Rail Voltage Output Power-on Reset to 0V Simultaneous Output Updating Wide power supply range (+2.7V to +5.5V) Industry's Smallest Package Power Down Modes Key Specifications ■ ■ ■ ■ ■ ■ ■ ■ Resolution INL DNL Settling Time Zero Code Error Full-Scale Error Supply Power — Normal — Power Down 12 bits ±8 LSB (max) +0.7 / −0.5 LSB (max) 8.5 µs (max) +15 mV (max) −0.75 %FS (max) 1.1 mW (3V) / 2.4 mW (5V) typ 0.3 µW (3V) / 0.8 µW (5V) typ Applications ■ ■ ■ ■ Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage & Current Sources Programmable Attenuators Pin Configuration 20173201 20173202 SPI™ is a trademark of Motorola, Inc. © 2007 National Semiconductor Corporation 201732 www.national.com DAC124S085 Ordering Information Order Numbers DAC124S085CISD DAC124S085CISDX DAC124S085CIMM DAC124S085CIMMX DAC124S085EVAL Temperature Range −40°C ≤ TA ≤ +105°C −40°C ≤ TA ≤ +105°C −40°C ≤ TA ≤ +105°C −40°C ≤ TA ≤ +105°C Package LLP LLP Tape-and-Reel MSOP MSOP Tape-and-Reel Evaluation Board (MSOP) Top Mark X67C X67C X66C X66C Block Diagram 20173203 www.national.com 2 DAC124S085 Pin Descriptions LLP MSOP Pin No. 1 2 3 4 5 6 7 8 Symbol VA VOUTA VOUTB VOUTC VOUTD GND VREFIN DIN Type Supply Analog Output Analog Output Analog Output Analog Output Ground Analog Input Digital Input Description Power supply input. Must be decoupled to GND. Channel A Analog Output Voltage. Channel B Analog Output Voltage. Channel C Analog Output Voltage. Channel D Analog Output Voltage. Ground reference for all on-chip circuitry. Unbuffered reference voltage shared by all channels. Must be decoupled to GND. Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow. 9 SYNC Digital Input 10 SCLK PAD (LLP only) Digital Input 11 Ground 3 www.national.com DAC124S085 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, VA Voltage on any Input Pin Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Consumption at TA = 25°C ESD Susceptibility (Note 5) Human Body Model Machine Model Junction Temperature Storage Temperature 6.5V −0.3V to 6.5V 10 mA 20 mA See (Note 4) 2500V 250V +150°C −65°C to +150°C Operating Ratings (Notes 1, 2) Operating Temperature Range Supply Voltage, VA Reference Voltage, VREFIN Digital Input Voltage (Note 7) Output Load SCLK Frequency −40°C ≤ TA ≤ +105°C +2.7V to 5.5V +1.0V to VA 0.0V to 5.5V 0 to 1500 pF Up to 40 MHz Package Thermal Resistances Package 10-Lead MSOP 10-Lead LLP θJA 240°C/W 250°C/W Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) Electrical Characteristics The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified. Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) 12 12 ±2.4 VA = 2.7V to 5.5V VA = 4.5V to 5.5V (Note 10) ZE FSE GE ZCED TC GE Zero Code Error Full-Scale Error Gain Error Zero Code Error Drift Gain Error Tempco VA = 3V VA = 5V IOUT = 0 IOUT = 0 All ones Loaded to DAC register +0.2 −0.1 ±0.15 +4 −0.1 −0.2 −20 −0.7 −1.0 0 VREFIN ±1 VA = 3V, IOUT = 200 µA ZCO Zero Code Output VA = 3V, IOUT = 1 mA VA = 5V, IOUT = 200 µA VA = 5V, IOUT = 1 mA VA = 3V, IOUT = 200 µA FSO Full Scale Output VA = 3V, IOUT = 1 mA VA = 5V, IOUT = 200 µA VA = 5V, IOUT = 1 mA Output Short Circuit Current (source) VA = 3V, VOUT = 0V, Input Code = FFFh VA = 5V, VOUT = 0V, Input Code = FFFh 1.3 6.0 7.0 10.0 2.984 2.934 4.989 4.958 -56 -69 ±8 +0.7 −0.5 ±0.5 +15 −0.75 −1.0 Units (Limits) Bits (min) Bits (min) LSB (max) LSB (max) LSB (min) LSB (max) mV (max) %FSR (max) %FSR µV/°C ppm/°C ppm/°C V (min) V (max) µA (max) mV mV mV mV V V V V mA mA STATIC PERFORMANCE Resolution Monotonicity INL DNL Integral Non-Linearity Differential Non-Linearity OUTPUT CHARACTERISTICS Output Voltage Range IOZ High-Impedance Output Leakage Current (Note 10) (Note 10) IOS www.national.com 4 DAC124S085 Symbol Parameter Conditions VA = 3V, VOUT = 3V, Input Code = 000h VA = 5V, VOUT = 5V, Input Code = 000h Available on each DAC output RL = ∞ RL = 2kΩ Typical (Note 9) 52 75 Limits (Note 9) Units (Limits) mA mA IOS Output Short Circuit Current (sink) IO CL ZOUT Continuous Output Current (Note 10) Maximum Load Capacitance DC Output Impedance Input Range Minimum 11 1500 1500 7.5 0.2 30 ±1 1.0 VA mA (max) pF pF Ω V (min) V (max) kΩ µA (max) V (max) V (max) V (min) V (min) pF (max) V (min) V (max) µA (max) µA (max) µA µA REFERENCE INPUT CHARACTERISTICS VREFIN Input Range Maximum Input Impedance LOGIC INPUT CHARACTERISTICS IIN VIL VIH CIN Input Current (Note 10) Input Low Voltage (Note 10) Input High Voltage (Note 10) Input Capacitance (Note 10) Supply Voltage Minimum Supply Voltage Maximum VA = 2.7V to 3.6V VA = 4.5V to 5.5V VA = 2.7V to 3.6V VA = 4.5V to 5.5V VA = 2.7V to 3.6V VA = 4.5V to 5.5V VA = 2.7V to 3.6V VA = 4.5V to 5.5V VA = 2.7V to 3.6V VA = 4.5V to 5.5V VA = 2.7V to 3.6V VA = 4.5V to 5.5V 360 480 330 440 0.10 0.15 1.1 2.4 1.0 2.2 0.3 0.8 3.6 5.5 1.0 1.0 1.7 3.6 VA = 3V VA = 5V VA = 3V VA = 5V 0.9 1.5 1.4 2.1 0.6 0.8 2.1 2.4 3 2.7 5.5 485 650 POWER REQUIREMENTS VA fSCLK = 30 MHz IN Normal Supply Current (output unloaded) fSCLK = 0 IPD Power Down Supply Current (output All PD Modes, unloaded, SYNC = DIN = 0V after (Note 10) PD mode loaded) µA (max) µA (max) mW (max) mW (max) mW mW µW (max) µW (max) fSCLK = 30 MHz PN Normal Supply Power (output unloaded) fSCLK = 0 PPD Power Down Supply Power (output All PD Modes, unloaded, SYNC = DIN = 0V after (Note 10) PD mode loaded) 5 www.national.com DAC124S085 A.C. and Timing Characteristics Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified. Symbol fSCLK ts SR Parameter SCLK Frequency Output Voltage Settling Time (Note 10) Output Slew Rate Glitch Impulse Digital Feedthrough Digital Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion tWU 1/fSCLK tCH tCL tSS tDS tDH tCFSR tSYNC Wake-Up Time SCLK Cycle Time SCLK High time SCLK Low Time SYNC Set-up Time prior to SCLK Falling Edge Data Set-Up Time prior to SCLK Falling Edge Data Hold Time after SCLK Falling Edge SCLK fall prior to rise of SYNC SYNC High Time VREFIN = 2.5V ± 0.1Vpp VREFIN = 2.5V ± 0.1Vpp input frequency = 10kHz VA = 3V VA = 5V Code change from 800h to 7FFh 400h to C00h code change RL = 2kΩ, CL = 200 pF Conductions Typical (Note 9) 40 6 1 12 0.5 1 3 160 70 0.8 0.5 25 7 7 4 1.5 1.5 0 6 33 10 10 10 3.5 3.5 3 10 Limits (Note 9) 30 8.5 Units

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