Description
CONFIDENTIAL CY7C9537B OC-48/STM-16 Framer–POSIC2G™ Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated — Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] — Complies with Bellcore GR253 rev.1, 1997[3] www.DataSheet4U.com — Channelized operation: supports 16xSTS-3c/VC4, 4xSTS-12c/VC4-4c, 2xSTS-24c/VC4-8c, and 1xSTS-48c/VC4-16c within OC-48 stream — Supports TUG3 mapping in SDH mode • Full duplex mapping of ATM cells over SONET/SDH — Complies with ITU-Standards I.432.2[4,5,6] • Full duplex mapping of packet-over-SONET/SDH: IETF RFC 1619/1662/2615 (HDLC/PPP)[7,8,9] • Generic Protocol Encapsulator/Decapsulator delineates packets/frames with length-CRC frame construct — Generic Framing Procedure (GFP) per ANSI T1X1.5[10,11,12] — GFP 268r1 — Simple Data Link (SDL) - IETF RFC2823 [13] — Cypress Hybrid Data Transport (HDT) [14] • User-programmable encapsulation • User-programmable clear channel transport • User-programmable SONET/SDH bypass • Programmable frame tagging engine for packet preclassification enables such features as — MPLS label lookup and tagging — PPP: LCP and NCP tagging — PPP control packets optionally sent to host CPU interface — MAC/layer 3 address look up and tagging • Programmable A1A2 processing bypass in Rx direction with frame sync input • Complete section overhead (SOH), line overhead (LOH), and path overhead (POH) processing • APS extraction, CPU interrupt generation, and programmable insertion of APS byte • Line side APS port interface • Provision for protection switching on SONET/SDH port • Programmable PRBS generator and receiver • Serial port to access line/section data communication channel (DCC) and voice communication channel (VCC) • Full duplex UTOPIA/OIF-SPI (POS-PHY) level 3 interface [15,16] • 16-bit/32-bit host CPU interface bus • JTAG and boundary scan • Glue-less interface with Cypress CYS25G0101DX OC-48 PHY • 0.18-µm CMOS, 504-pin BGA package • +1.8V for core, +3.3V for LVTTL I/O, +1.5V/+3.3V for HSTL/LVPECL I/O supply, and +0.75V/2.0V reference Applications • Multiservice nodes • ATM switches and routers • Packet routers • Multi-service routers • SONET/SDH add-drop mux for packet/data applications • SONET/SDH/ATM/POS test equipment Notes: 1. ITU-T Recommendation G.707. “Network Node Interface for the Synchronous Digital Hierarchy.” 1996. 2. ITU-T Recommendation G.783. “Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks.” 2000. 3. Bellcore Publication GR-253-Core. “Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria.” 1997. 4. ITU-T Recommendation I.432.3. “B-ISDN User-Network Interface—Physical Layer Specification: 1544 kbit/s and 2048 kbit/s operation.” 1999. 5. American National Standards Institute. “Synchronous Optical Network (SONET)—Basic Description including Multiplex Structure, Rates and Formats.” ANSI T1.105–1995. 6. American National Standards Institute. “Synchronous Optical Network (SONET)—Payload Mappings.” ANSI T1.105.02–1998. 7. Simpson, W. “PPP Over SONET/SDH.” RFC 1619. May 1994. 8. Simpson, W., ed. “PPP in HDLC-like Framing.” RFC 1662. Daydreamer. July 1994. 9. Malis, A. and Simpson, W. “PPP Over SONET/SDH.” RFC 2615. June 1999. 10. Hernandez-Valencia, E. Lucent Technologies. “A Generic Frame Format for Data Over SONET (DoS).” March 2000. 11. Gorshe, C. and Steven. T1X1.5/99-204, T1 105.02. Draft Text for Mapping IEEE 802.3 Ethernet MAC Frames to SONET Payload. July 1999. 12. Hernandez-Valencia, E. Lucent Technologies. T1X1.5/2000-209. “Generic Framing Procedure (GFP) Specification.” October 9–13, 2000. 13. Carlson, J., P. Langner, E.J. Hernandez-Valencia, and J. Manchester. “PPP over Simple Data Link (SDL) using SONET/SDH with ATM-like Framing.” rfc2823.txt, May 2000. 14. Pankaj, K. “A Hybrid Data Transport Protocol for Optical Networks.” RFC draft-jha-optical-hdt-00.txt. November 2000. Cypress Semiconductor Corporation Document #: 38-02079 Rev. *F • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised May 3, 2005 CONFIDENTIAL CY7C9537B LAN & CBR W AN D a ta L in k D e v ic e or ATM SAR CY7C9537B U T O P IA P O S -P H Y HBST P O S IC E /O CYS25G 0101DX O C -4 8 T ra n s c e iv e r O /E CPU www.DataSheet4U.com Figure 1. POSIC2G System Application Diagram POSIC2G Logic Block Diagram SONETTX_PAROUT TXFRAME_PULSE TX SONET Line Interface POHSDIN TOHSDIN TE1STROBE TE2STROBE SONET Transmit SONET Framing Overhead Processor Bypass Pointer Processor Transmit SONET Text Framer TXCLKI TXCLKOUT TXD[31:0] RXCLKs RXD[31:0] LFI RXFRAME RXCLK I _PULSE RX SONET Line Interface Receive SONET Receiv e De-Framer SONET SONE Receive SONET Framing T Overhead Overhe Processor Bypass ad Pointer Insertio Processor n SONETRXPARIN Clk2MHz Clk16MHz POHSDOUT RPOHSTART TPOHSTART RE1STROBE RE2STROBE TOHSDOUR TX ATM Encapsulator TX TX Generic HDLC Protocol Encapsulator Encapsulator RX RX RX Generic ATM HDLC Protocol Decapsulator Decapsulator Decapsulator Programmable Frame Tagging Engine TCK TRST TDI TMS TDO General Pins JTAG Interface Transmit UTOPIA/SPI-3 Interface CPU Interface Receive UTOPIA/SPI-3 Interface RST_n SYSCLK RSTOUT_n CLKOUT TEST[2:0] MISC[15:0] POSIC_OEN SCAN_ENA TFCLK TERR TDAT[31:0] TPRTY TADD[3:0] TMOD[1:0] TSOP TEOP STPA PTCA TENB TSX DTCA[3:0] CpuClk CpuTs_n/CpuAds_n CpuSel CpuBlast_n CpuTa_n ChipSel CpuInt CpuClkFail CpuWrRd CpuAD[31:0] Mode RVAL RENB RFCLK RDAT[31:0] RADD[70] RMOD[1:0] RPRTY RERR REOR RSOP RCA RSX Document #: 38-02079 Rev. *F Page 2 of 43 CONFIDENTIAL Overview The CY7C9537B (POSIC2G) is a highly integrated SONET/SDH framer device for transport of ATM and IP packets over SONET/SDH links. It features special functions and architecture to support next-generation optical networking protocols for both SONET/SDH and direct data-over-fiber networks. UTOPIA level 3, OIF-SPI (POS-PHY) level 3 and high-bandwidth synchronous transfer (HBST) interfaces are provided on the system side. POSIC2G performs complete SOH, LOH, and POH processing. Complete access to all overhead bytes is provided through register access via the host CPU interface. Access to selected overhead bytes is also available through the serial port. Optional frame sync input and Transport Overhead www.DataSheet4U.com (TOH) bypass enables better interface with SPE/VC switched streams. POSIC2G supports packet over SONET/SDH as PPP in HDLC-like frame as per IETF rfc 1619/1662/2615 (PPP). POSIC2G also supports full-duplex ATM over SONET/SDH transport in compliance with ITU I432.2. The Generic Protocol Encapsulator/Decapsulator features wire rate framing, frame delineation and deframing with length-CRC pair header construct. Optional payload scrambling/descrambling and payload FCS are also provided. This enables POSIC2G to support many new-generation protocols like SDL, GFP, and HDT over SONET/SDH. Clear channel mode enables transport of any raw byte streams on selected channels, while the rest of the channels are transporting data through any one of encapsulation/decapsulation engines. The Programmable Frame Tagging Engine enables wire-rate tagging of packets/frames. For new-generation networking features such as MPLS, this engine can be programmed to tag based on existence/lack of specific label/field values, in the first 64 bytes of each packet. This way, packets are tagged for a variety of conditions, all programmable by the user, enabling sorting of packets in the incoming data stream and buffering packets accordingly. In a PPP application, control packets can optionally be sent over the host CPU interface directly. SONET/SDH bypass mode allows use of this device for data transport in non-SONET/SDH point-to-point and mesh optical networks. CY7C9537B POSIC2G supports three basic types of encapsulation, namely (i) ATM, (ii) HDLC frame, and (iii) frames with length-CRC pair header construct based delineation. SDL, GFP and HDT frames are delineated based on length-CRC pair header construct and they are supported by POSIC2G. Clear channel or transparent mode (no encapsulation) is also supported. While in operation, only one type of encapsulation can be enabled for all channels. Some or all of the channels can be programmed as clear channels. For Clear Channels, the encapsulator engine will bypass the encapsulation and pass the packets without any processing to the next block. Since POSIC2G does not have a packet storage memory on-chip, a channel bandwidth balanced packet flow is expected from the system side. To enable such a balanced transfer, POSIC2G has internal FIFO of 512 bytes per channel. The status of FIFO is provided through pins to the link layer. Finally, the SONET/SDH framer inserts the packet/cells into the SONET/SDH frame. All overhead bytes are added. All alarm bits and status bits are inserted based on the status of incoming frames as well as programming done by the host CPU. The scrambler meets relevant standards and can optionally be disabled. Frames are finally sent out on the fiber side interface. If programmed to do so, the SONET/SDH framer can be bypassed and encapsulated packets/frames can be sent directly to the fiber-side interface. Receive In the receive direction, SONET/SDH frames are received from the fiber side. Data packets/frames are extracted from the payload and passed onto the selected decapsulator engine. If the SONET/SDH framer is bypassed, the incoming data stream is directly passed over to the decapsulator engine. Data packets/frames are then decapsulated and sent to the Programmable Frame Tagging Engine. They are then analyzed and tagged before being sent out to the system side via the UTOPIA, OIF-SPI level 3, or HBST interface. Tagging of frames is optional. SONET/SDH frames entering from the fiber side are synchronized and the frame bou

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