CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Features
• High-speed, low-power, first-in, first-out (FIFO) memories • 64 x 9 (CY7C4421V) • 256 x 9 (CY7C4201V) • 512 x 9 (CY7C4211V) • 1K x 9 (CY7C4221V) • 2K x 9 (CY7C4231V) • 4K x 9 (CY7C4241V) • 8K x 9 (CY7C4251V) • High-speed 66-MHz operation (15-ns read/write cycle time) • Low power (ICC = 20 mA) • 3.3V operation for low power consumption and easy integration into low-voltage systems • 5V-tolerant inputs VIH max= 5V • Fully asynchronous and simultaneous read and write operation • Empty, Full, and Programmable Almost Empty and Almost Full status flags • TTL compatible • Output Enable (OE) pin • Independent read and write enable pins • Center power and ground pins for reduced noise • Width expansion capability • Space saving 32-pin 7 mm × 7 mm TQFP • 32-pin PLCC
Functional Description
The CY7C42X1V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All are nine bits wide. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a Free-Running Clock (WCLK) and two Write Enable pins (WEN1, WEN2/LD). When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a Free-Running Read Clock (RCLK) and two Read Enable Pins (REN1, REN2). In addition, the CY7C42X1V has an Output Enable Pin (OE). The Read (RCLK) and Write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 66 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data.
Logic Block Diagram
D0 − 8
Pin Configuration
PLCC Top View
4 3 2 1 32 3130 29 5 28 6 27 7 26 8 9 25 10 24 11 23 22 12 21 13 141516 171819 20 EF FF Q0 Q1 Q2 Q3 Q4 D2 D3 D4 D5 D6 D7 D8 D1 D0 PAF PAE GND REN1 RCLK REN2 OE EF PAE PAF FF
INPUT REGISTER
WCLK WEN1 WEN2/LD FLAG PROGRAM REGISTER WRITE CONTROL FLAG LOGIC Dual Port RAM Array 64 x 9 WRITE POINTER 8Kx 9 READ POINTER
RS WEN1 WCLK WEN2/LD V CC Q8 Q7 Q6 Q5
TQFP Top View
D4 D5 D6 D7 D8 RS 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 OE EF FF Q0 Q1 Q2 Q3 Q4 D2 D3 1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 RS RESET LOGIC D1 D0 PAF PAE GND REN1 RCLK REN2 WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5
THREE-ST ATE OUTPUTREGISTER OE Q0 − 8
READ CONTROL
RCLK REN1 REN2
Cypress Semiconductor Corporation Document #: 38-06010 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134 • 408-943-2600 Revised August 22, 2003
CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Selection Guide
CY7C42X1V-15 Maximum Frequency Maximum Access Time Minimum Cycle Time Minimum Data or Enable Set-up Minimum Data or Enable Hold Maximum Flag Delay Active Power Supply Current CY7C4421V Density 64 x 9 Commercial CY7C4201V 256 x 9 CY7C4211V 512 x 9 66.7 11 15 4 1 10 20 CY7C4221V 1K x 9 CY7C42X1V-25 40 15 25 6 1 15 20 CY7C4231V 2K x 9 CY7C42X1V-35 28.6 20 35 7 2 20 20 CY7C4241V 4K x 9 Unit MHz ns ns ns ns ns mA CY7C4251V 8K x 9
Pin Definitions
Signal Name D0−8 Q0−8 WEN1 Description Data Inputs Data Outputs Write Enable 1 I/O I O I Data Inputs for 9-bit bus. Data Outputs for 9-bit bus. The only write enable when device is configured to have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH. If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin operates as a control to write or read the programmable flag offsets. WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. Enables the device for Read operation. The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag offset register. When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. When FF is LOW, the FIFO is full. FF is synchronized to WCLK. When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO. When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. Resets device to empty condition. A reset is required before an initial read or write operation after power-up. When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the RCLK. The flags denoting Almost Full and Full states are updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle All configurations are fabricated using an advanced 0.65m P-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Description
WEN2/LD Dual Mode Pin
Write Enable 2 Load
I I
REN1, REN2 WCLK
Read Enable Inputs Write Clock
I I
RCLK
Read Clock
I
EF FF PAE PAF RS OE
Empty Flag Full Flag Programmable Almost Empty Programmable Almost Full Reset Output Enable
O O O O I I
Functional Description (continued)
The CY7C42X1V provides four status pins: Empty, Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty-7 and Full-7. The flags are synchronous, i.e., they change state relative to either the Read Clock (RCLK) or the Write Clock (WCLK).
Document #: 38-06010 Rev. *A
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Architecture
The CY7C42X1V consists of an array of 64 to 8K words of nine bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF.) Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin. The FIFO is configured at Reset to have programmable flags or to have two write enables, which allows for depth expansion. If Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset (RS=LOW), this pin operates as a second write enable pin. If the FIFO is configured to have two write enables, when Write Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK.) Data is stored in the RAM array sequentially and independently of any on-going read operation.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs (Q0-8) go LOW tRSF after the rising edge of RS. In order for the FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or write while RS is LOW. All flags are guaranteed to be valid tRSF after RS is taken LOW.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load (LD) enable for flag offset programming. In this configuration, WEN2/LD can be used to access the four 8-bit offset registers contained in the CY7C42X1V for writing or reading data to these registers. When the device is configured for programmable flags and both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition of WCLK writes data from the data inputs to the empty offset Least Significant Bit (LSB) register. The second, third, and fourth LOW-to-HIGH transitions of WCLK store data in the empty offset Most Significant Bit (MSB) register, full offset LSB register, and full offset MSB register, respectively, when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD and WEN1 are LOW writes data to the empty LSB register again. Figure 1 shows the register sizes and default values for the various device types. It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written; then by bringing the WEN2/LD input HIGH, the FIFO is returned to normal read and write operation. The next time WEN2/LD is brought LOW, a write operation stores data in the next offset register in sequence. The contents of the offset registers can be read to the data outputs when WEN2/LD is LOW and both REN1 and REN2 are LOW. LOW-to-HIGH transitions of RCLK read register contents to the data outputs. Writes and reads should not be performed simultaneously on the offset registers.
FIFO Operation
When the WEN1 signal is active LOW and WEN2 is active HIGH, data present on the D0-8 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN1 and REN2 signals are active LOW, data in the FIFO memory will be presented on the Q0-8 outputs. New data will be presented on each rising edge of RCLK while REN1 and REN2 are active. REN1 and REN2 m
