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CY7C1471V25 CY7C1473V25 CY7C1475V25
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture
Features
• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Can support up to 133-MHz bus operations with zero wait states • Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 2.5V/1.8V I/O power supply • Fast clock-to-output times — 6.5 ns (for 133-MHz device) — 8.5 ns (for 100-MHz device) • Clock Enable (CEN) pin to enable clock and suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • Offered in JEDEC-standard lead-free 100 TQFP, and 165-ball fBGA packages for CY7C1471V25 and CY7C1473V25. 209-ball fBGA package for CY7C1475V25. • Three chip enables for simple depth expansion. • Automatic Power-down feature available using ZZ mode or CE deselect. • JTAG boundary scan for BGA and fBGA packages • Burst Capability—linear or interleaved burst order • Low standby power
Functional Description[1]
The CY7C1471V25, CY7C1473V25 and CY7C1475V25 are 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1471V25, CY7C1473V25 and CY7C1475V25 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.
Selection Guide
133 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 305 120 100 MHz 8.5 275 120 Unit ns mA mA
Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05287 Rev. *E
•
3901 North First Street
•
San Jose, CA 95134 • 408-943-2600 Revised December 5, 2004
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Logic Block Diagram – CY7C1471V25 (2M x 36)
A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0 Q1 A1' A0' Q0
CY7C1471V25 CY7C1473V25 CY7C1475V25
BURST LOGIC
ADV/LD BWA BWB BWC BWD WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
O U T P U T B U F F E R S E
DQs DQPA DQPB DQPC DQPD
OE CE1 CE2 CE3 ZZ
INPUT E REGISTER READ LOGIC
SLEEP CONTROL
Logic Block Diagram – CY7C1473V25 (4M x 18)
A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER
A1 D1 A0 D0
BURST LOGIC
Q1 A1' A0' Q0
ADV/LD BWA BWB WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
O U T P U T B U F F E R S E
DQs DQPA DQPB
WE
OE CE1 CE2 CE3
ZZ
INPUT E REGISTER READ LOGIC
SLEEP CONTROL
Document #: 38-05287 Rev. *E
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1
CY7C1471V25 CY7C1473V25 CY7C1475V25
Logic Block Diagram – CY7C1475V25 (1M x 72)
A0, A1, A MODE CLK CEN C
WRITE ADDRESS REGISTER 1
ADDRESS REGISTER 0
A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C
WRITE ADDRESS REGISTER 2
ADV/LD BWa BWb BWc BWd BWe BWf BWg BWh
WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS
MEMORY ARRAY
S E N S E A M P S
O U T P U T R E G I S T E R S
D A T A S T E E R I N G
O U T P U T B U F F E R S
E
E
DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh
WE
INPUT REGISTER 1 E INPUT REGISTER 0 E
OE CE1 CE2 CE3 ZZ
READ LOGIC
Sleep Control
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Pin Configurations
100-lead TQFP
BWD BWC BWB BWA CEN CLK ADV/LD
CY7C1471V25 CY7C1473V25 CY7C1475V25
CE1
CE2
CE3
VDD
VSS
WE
OE
A 82
A
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
A
BYTE C
BYTE D
DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38
81
A
CY7C1471V25
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
44 45 46 47 48 49 50
DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA
BYTE B
BYTE A
39
40
41
42
A1
A0
VSS
MODE
NC / 288M
NC / 144M
VDD
A
A
A
A
43
A
A
A
A
Document #: 38-05287 Rev. *E
A
A
A
A
A
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Pin Configurations (continued)
100-lead TQFP
BWB BWA CEN CLK ADV/LD
CY7C1471V25 CY7C1473V25 CY7C1475V25
CE1
CE2
CE3
VDD
VSS
WE
OE
NC
NC
A 82
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
A
83
A
NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC
BYTE B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38
81
A
CY7C1473V25
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
44 45 46 47 48 49 50
A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC
BYTE A
39
40
41
42
A1
A0
VSS
MODE
NC / 288M
NC / 144M
VDD
A
A
A
A
43
A
A
A
Document #: 38-05287 Rev. *E
A
A
A
A
A
A
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Pin Configurations (continued)
165-ball fBGA (3 Chip Enable with JTAG)
CY7C1471V25 (2M x 36)
CY7C1471V25 CY7C1473V25 CY7C1475V25
1 A B C D E F G H J K L M N P R
NC / 288M NC DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE
2
A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC
A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
CEN WE
8
ADV/LD OE
9
A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
10
A
11
NC NC / 144M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA NC A
A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
A
A
A
CY7C1473V25 (4M x 18)
1 A B C D E F G H J K L M N P R
NC / 288M NC NC NC NC NC NC NC DQB DQB DQB DQB DQPB NC MODE
2
A A NC DQB DQB DQB DQB NC NC NC NC NC NC
A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
CEN WE
8
ADV/LD OE
9
A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
10
A
11
A NC / 144M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC NC A
A NC NC NC NC NC NC DQA DQA DQA DQA NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
A
A
A
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Pin Configurations (continued) 209-ball PBGA
CY7C1475V25 (1M × 72)
1 A B C D E F G H J K L M N P R T U V W
DQg DQg DQg DQg DQPg DQc DQc DQc DQc NC DQh DQh DQh DQh DQPd DQd DQd DQd DQd
CY7C1471V25 CY7C1473V25 CY7C1475V25
2
DQg DQg DQg DQg DQPc DQc DQc DQc DQc NC DQh DQh DQh DQh DQPh DQd DQd DQd DQd
3
A BWSc BWSh VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS
4
CE2 BWSg BWSd NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI
5
A NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC
6
ADV/LD WE CE1 OE VDD NC NC NC NC CEN NC NC NC ZZ VDD MODE A A1 A0
7
A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A
8
CE3 BWSb BWSe NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO
9
A BWSf BWSa VSS VDDQ VSS VDDQ VSSQ VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK
10
DQb DQb DQb DQb DQPf DQf DQf DQf DQf NC DQa DQa DQa DQa DQPa DQe DQe DQe DQe
11
DQb DQb DQb DQb DQPb DQf DQf DQf DQf NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe
A
A A
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Pin Definitions
Name A0, A1, A BWA, BWB, BWC, BWD, BWE, BWF, BWG, BWH WE ADV/LD I/O InputSynchronous InputSynchronous Description
CY7C1471V25 CY7C1473V25 CY7C1475V25
Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter. Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK.
InputSynchronous InputSynchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burs
