(CY7C147xV25) 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM

www.DataSheet4U.com PRELIMINARY CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200, and 167 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write capability • Single 2.5V power supply • 2.5V/1.8V I/O operation • Fast clock-to-output times — 3.0 ns (for 250-MHz device) — 3.0 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • CY7C1470V25 and CY7C1472V25 available in lead-free 100 TQFP, and 165 fBGA packages. CY7C1474V25 available in 209-ball fBGA package. • Compatible with IEEE 1149.1 JTAG Boundary Scan • Burst capability—linear or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1470V25/ CY7C1472V25/CY7C1474V25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1470V25/CY7C1472V25/CY7C1474V25 are pin-compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BWa–BWh for CY7C1474V25, BWa–BWd for CY7C1470V25 and BWa–BWb for CY7C1472V25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Logic Block Diagram-CY7C1470V25 (2M x 36) A0, A1, A MODE CLK CEN ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 C ADV/LD BWa BWb BWc BWd WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G O U T P U T B U F F E R S E DQs DQPa DQPb DQPc DQPd E INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 ZZ READ LOGIC SLEEP CONTROL Cypress Semiconductor Corporation Document #: 38-05290 Rev. *E • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised December 5, 2004 www.DataSheet4U.com PRELIMINARY Logic Block Diagram-CY7C1472V25 (4M x 18) A0, A1, A MODE CLK CEN C WRITE ADDRESS REGISTER 1 CY7C1470V25 CY7C1472V25 CY7C1474V25 ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 ADV/LD BWa BWb WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQPa DQPb E E INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 ZZ READ LOGIC Sleep Control Logic Block Diagram-CY7C1474V25 (1M x 72) A0, A1, A MODE CLK CEN ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 C ADV/LD BWa BWb BWc BWd BWe BWf BWg BWh WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G O U T P U T B U F F E R S E E DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh WE INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 ZZ READ LOGIC Sleep Control Selection Guide CY7C1470V25-250 CY7C1472V25-250 CY7C1474V25-250 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 3.0 450 120 CY7C1470V25-200 CY7C1472V25-200 CY7C1474V25-200 3.0 450 120 CY7C1470V25-167 CY7C1472V25-167 CY7C1474V25-167 3.4 400 120 Unit ns mA mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05290 Rev. *E Page 2 of 27 www.DataSheet4U.com PRELIMINARY Pin Configurations 100-pin TQFP Packages A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A CY7C1470V25 CY7C1472V25 CY7C1474V25 A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A NC DQPb NC DQb NC DQb VDDQ VDDQ VSS VSS NC DQb DQb NC DQb DQb DQb DQb VSS VSS VDDQ V DDQ A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb NC DQa VSS VSS VDDQ VDDQ NC DQa DQa NC DQPa NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC CY7C1470V25 (2M × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C1472V25 (4M × 18) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 E(288) E(144) VSS VDD A A A A A A A A A MODE A A A A A1 A0 E(288) E(144) Document #: 38-05290 Rev. *E VSS VDD A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 27 www.DataSheet4U.com PRELIMINARY Pin Configurations (continued) 165-Ball fBGA Pinout CY7C1470V25 CY7C1472V25 CY7C1474V25 1 A B C D E F G H J K L M N P R E(288) NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE 2 A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A CY7C1470V25 (2M × 36) 4 5 6 7 BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 8 ADV/LD 9 A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC E(144) DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS CE3 CLK CEN WE OE A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A A A CY7C1472V25 (4M × 18) 1 A B C D E F G H J K L M N P R E(288) NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE 2 A A NC DQb DQb DQb DQb NC NC NC NC NC NC A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 CEN WE VSS VSS 8 ADV/LD 9 A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A 11 A E(144) DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 OE VSS A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK A A A Document #: 38-05290 Rev. *E Page 4 of 27 www.DataSheet4U.com PRELIMINARY Pin Configurations (continued) 209-ball Bump BGA 1 A B C D E F G H J K L M N P R T U V W DQg DQg DQg DQg DQPg DQc DQc DQc DQc NC DQh DQh DQh DQh DQPd DQd DQd DQd DQd CY7C1470V25 CY7C1472V25 CY7C1474V25 2 DQg DQg DQg DQg DQPc DQc DQc DQc DQc NC DQh DQh DQh DQh DQPh DQd DQd DQd DQd 3 A BWSc BWSh VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS 4 CE2 BWSg BWSd NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI CY7C1474V25 (1M x 72) 5 6 7 A NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A ADV/LD WE CE1 OE VDD NC NC NC NC CEN NC NC NC ZZ VDD MODE A A1 A0 A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A 8 CE3 BWSb BWSe NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A BWSf BWSa VSS VDDQ VSS VDDQ VSSQ VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK 10 DQb DQb DQb DQb DQPf DQf DQf DQf DQf NC DQa DQa DQa DQa DQPa DQe DQe DQe DQe 11 DQb DQb DQb DQb DQPb DQf DQf DQf DQf NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe Pin Definitions Pin Name A0 A1 A BWa BWb BWc BWd BWe BWf BWg BWh WE I/O Type InputSynchronous InputSynchronous Pin Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh. InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Document #: 38-05290 Rev. *E Page 5 of 27 www.DataSheet4U.com PRELIMINARY Pin Definitions (continued) Pin Name ADV/LD I/O Type InputSynchronous Pin Description CY7C1470V25 CY7C1472V25 CY7C1474V25 Advance/Load Input used to advance the