(CY7C144xAV33) Sync SRAM

www.DataSheet4U.com PRELIMINARY CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200,167 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 3.2 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single Cycle Chip Deselect • Offered in JEDEC-standard 100-pin TQFP, 165-Ball fBGA and 209-Ball fBGA packages • Also available in lead-free packages • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option Intel® Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1,048,576 x 36, 2,097,152 x 18 and 524,288 x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 475 100 200 MHz 3.2 425 100 167 MHz 3.4 375 100 Unit ns mA mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3, CE2 are for TQFP and 165 fBGA package only. Cypress Semiconductor Corporation Document #: 38-05383 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 31, 2005 PRELIMINARY Logic Block Diagram – CY7C1440AV33 (1 Mbit x 36) A0, A1, A CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 ADDRESS REGISTER 2 A[1:0] MODE ADV CLK Q1 ADSC ADSP BWD DQD ,DQPD BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE REGISTER DQA ,DQPA BYTE WRITE REGISTER BURST COUNTER CLR AND Q0 LOGIC DQD ,DQPD BYTE WRITE DRIVER DQC ,DQPC BYTE WRITE DRIVER DQB ,DQPB BYTE WRITE DRIVER DQA ,DQPA BYTE WRITE DRIVER BWC MEMORY ARRAY SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E BWB DQs DQPA DQPB DQPC DQPD BWA BWE GW CE1 CE2 CE3 OE ENABLE REGISTER PIPELINED ENABLE INPUT REGISTERS ZZ SLEEP CONTROL Logic Block Diagram – CY7C1442AV33 (2 Mbit x 18) A0, A1, A MODE ADDRESS REGISTER 2 A[1:0] ADV CLK BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP DQB,DQPB WRITE REGISTER DQB,DQPB WRITE DRIVER MEMORY ARRAY BWA BWE GW CE1 CE2 CE3 OE ENABLE REGISTER DQA,DQPA WRITE REGISTER DQA,DQPA WRITE DRIVER SENSE AMPS BWB OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQPA DQPB PIPELINED ENABLE INPUT REGISTERS ZZ SLEEP CONTROL Document #: 38-05383 Rev. *B Page 2 of 27 PRELIMINARY Logic Block Diagram – CY7C1446AV33 (512K x 72) A0, A1,A CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 ADDRESS REGISTER A[1:0] MODE ADV CLK Q1 BINARY COUNTER CLR Q0 ADSC ADSP BWH DQH, DQPH WRITE DRIVER DQF, DQPF WRITE DRIVER DQF, DQPF WRITE DRIVER DQE, DQPE WRITE DRIVER DQD, DQPD WRITE DRIVER DQH, DQPH WRITE DRIVER DQG, DQPG WRITE DRIVER DQF, DQPF WRITE DRIVER DQE, DQPE BYTE “a” WRITE DRIVER DQD, DQPD WRITE DRIVER DQC, DQPC WRITE DRIVER SENSE AMPS BWG BWF BWE MEMORY ARRAY BWD BWC DQC, DQPC WRITE DRIVER OUTPUT REGISTERS BWB DQB, DQPB WRITE DRIVER DQB, DQPB WRITE DRIVER DQA, DQPA WRITE DRIVER OUTPUT BUFFERS E BWA BWE GW CE1 CE2 CE3 OE DQA, DQPA WRITE DRIVER ENABLE REGISTER PIPELINED ENABLE INPUT REGISTERS DQs DQPA DQPB DQPC DQPD DQPE DQPF DQPG DQPH ZZ SLEEP CONTROL Document #: 38-05383 Rev. *B Page 3 of 27 PRELIMINARY Pin Configurations 100-pin TQFP Pinout A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPC DQC DQc VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1440AV33 (1 Mbit x 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1442AV33 (2 Mbit x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 NC / 72M A VSS VDD MODE A A A A A1 A0 NC / 72M A VSS VDD A A A A A A A A A Document #: 38-05383 Rev. *B A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 4 of 27 PRELIMINARY Pin Configurations (continued) 165-ball fBGA CY7C1440AV33 (1 Mbit x 36) CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 1 A B C D E F G H J K L M N P R NC / 288M NC DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE 2 A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC NC / 72M A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 BWE GW 8 ADSC OE VSS VDD 9 ADV ADSP 10 A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A 11 NC NC / 144M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A VDD VDD VDD VDD VDD VDD VDD VDD VSS A A A CY7C1442AV33 (2 Mbit x 18) 1 A B C D E F G H J K L M N P R NC / 288M NC NC NC NC NC NC NC DQB DQB DQB DQB DQPB NC MODE 2 A A NC DQB DQB DQB DQB NC NC NC NC NC NC NC / 72M A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 BWE GW 8 ADSC OE 9 ADV ADSP 10 A A NC NC NC NC NC NC DQA DQA DQA DQA NC A A 11 A NC / 144M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A A A Document #: 38-05383 Rev. *B Page 5 of 27 PRELIMINARY Pin Configurations (continued) 209-ball fBGA CY7C1446AV33 (512K × 72) 1 A B C D E F G H J K L M N P R T U V W 2 3 A BWSC BWSH VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 4 CE2 BWSG BWSD NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI 5 6 7 ADV A NC GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A 8 CE3 BWSB BWSE NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A BWSF BWSA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS A A TCK 10 11 DQG DQG DQG DQG DQPG DQC DQC DQC DQC NC DQG DQG DQG DQG DQPC DQC DQC DQC DQC NC ADSP ADSC NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A BW CE1 OE VDD NC NC NC NC VSS NC NC NC ZZ VDD MODE A A1 A0 DQB DQB DQB DQB DQPF DQF DQF DQF DQF NC DQB DQB DQB DQB DQPB DQF DQF DQF DQF NC DQH DQH DQH DQH DQPD DQD DQD DQD DQD DQH DQH DQH DQH DQPH DQD DQD DQD DQD DQA DQA DQA DQA DQPA DQE DQE DQE DQE DQA DQA DQA DQA DQPE DQE DQE DQE DQE Pin Definitions Name A0, A1, A I/O InputSynchronous InputSynchronous Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled active. A1: A0 are fed to the two-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. BWA, BWB, BWC, BWD, BWE, BWF, BWG, BWH GW InputSynchronous InputSynchronous InputClock InputSynchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This s