CY7C1382CV25 (Cypress Semiconductor) - (CY7C1380CV25 / CY7C1382CV25) 512K x 36/1M x 18 Pipelined SRAM (CY7C1382CV25.pdf)

Cypress Semiconductor

Description
www.DataSheet4U.com 380CV25 PRELIMINARY CY7C1380CV25 CY7C1382CV25 512K x 36/1M x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 250, 225, 200, 167 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns Optimal for depth expansion Single 2.5V ±5% power supply Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed Write cycle Burst control pins (interleaved or linear burst sequence) • Automatic power-down available using ZZ mode or CE deselect • Available in 119-ball bump BGA, 165-ball FBGA and 100-pin TQFP packages • JTAG boundary scan for BGA packaging version (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE), burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb, BWc, BWd and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and burst mode control (MODE). The data (DQa,b,c,d) and the data parity (DQPa,b,c,d) outputs, enabled by OE, are also asynchronous. DQa,b,c,d and DPa,b,c,d apply to CY7C1380CV25 and DQa,b and DPa,b apply to CY7C1382CV25. a, b, c, d each are of 8 bits wide in the case of DQ and 1 bit wide in the case of DP. Addresses and chip enables are registered with either address status processor (ADSP) or address status controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa and DPa. BWb controls DQb and DPb. BWc controls DQc and DPd. BWd controls DQd and DPd. BWa, BWb BWc, and BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. Write pass-through capability allows written data available at the output for the next Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. All inputs and outputs of the CY7C1380CV25 and the CY7C1382CV25 are JEDEC standard JESD8-5 compatible. Functional Description The Cypress Synchronous Burst SRAM family employs highspeed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors. The CY7C1382CV25 and CY7C1380CV25 SRAMs integrate 1,048,576x18 and 524,288x36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input Selection Guide 250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Shaded areas contain advance information. 225 MHz 2.8 325 70 200 MHz 3.0 300 70 167 MHz 3.4 275 70 Unit ns mA mA 2.6 350 70 Cypress Semiconductor Corporation Document #: 38-05240 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 20, 2002 PRELIMINARY CY7C1380CV25 - 512K x 36 CLK ADV ADSC ADSP A[18:0] GW BWE BW d BWc D BWb D BWa CE1 CE2 CE3 D CY7C1380CV25 CY7C1382CV25 MODE (A[1;0]) 2 BURST Q0 CE COUNTER Q1 CLR Q ADDRESS CE REGISTER D DQd, DPd BYTEWRITE REGISTERS DQc, DPc BYTEWRITE REGISTERS DQb, DPb BYTEWRITE REGISTERS DQa, DPa BYTEWRITE REGISTERS ENABLE CE REGISTER Q 17 19 19 17 D 512KX36 MEMORY ARRAY D Q Q Q 36 Q 36 D ENABLE DELAY Q REGISTER OE ZZ SLEEP CONTROL OUTPUT REGISTERS CLK INPUT REGISTERS CLK DQa,b,c,d DPa,b CY7C1382CV25 - 1M X 18 CLK ADV ADSC ADSP A[19:0] GW BWE BW b BWa MODE (A[1;0]) 2 BURST Q0 CE COUNTER Q1 CLR Q ADDRESS CE REGISTER D DQb, DPb BYTEWRITE REGISTERS DQa, DPa BYTEWRITE REGISTERS Q 18 20 20 18 D 1M X 18 MEMORY ARRAY D Q CE1 CE2 CE3 18 D ENABLE CE CE REGISTER Q 18 D ENABLE DELAY Q REGISTER OE ZZ SLEEP CONTROL OUTPUT REGISTERS CLK INPUT REGISTERS CLK DQa,b DPa,b Document #: 38-05240 Rev. *A Page 2 of 33 PRELIMINARY Pin Configurations 100-Pin TQFP Top View A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A CY7C1380CV25 CY7C1382CV25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC,DQPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd NC,DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1380CV25 (512K X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC,DQPb DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa DQa DQa VSSQ VDDQ DQa DQa NC,DQPa NC NC NC VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DPb NC VSSQ VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1382CV25 (1M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DPa DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC MODE A A A A A1 A0 NC NC VSS VDD A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 NC NC VSS VDD Document #: 38-05240 Rev. *A A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 33 PRELIMINARY Pin Configurations (continued) 119-Ball BGA CY7C1380CV25 CY7C1382CV25 CY7C1380CV25 (512K x 36) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 A A A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A 72M TMS 3 A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A TCK 5 A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A A A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A 36M NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ CY7C1382CV25 (1M x 18) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC 72M VDDQ 2 A A A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS 3 A A A VSS VSS VSS BWb VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD 36M TCK 5 A A A VSS VSS VSS VSS VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A A A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC 7 VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ Document #: 38-05240 Rev. *A Page 4 of 33 PRELIMINARY Pin Configurations (continued) 165-Ball Bump FBGA CY7C1380CV25 (512K x 36) - 11 x 15 FBGA 1 A B C D E F G H J K L M N P R NC NC DPc DQc DQc DQc DQc NC DQd DQd DQd DQd DPd NC MODE CY7C1380CV25 CY7C1382CV25 2 A A NC DQc DQc DQc DQc VSS DQd DQd DQd DQd NC 72M 36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC 144M DPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DPa A A CY7C1382CV25 (1M x 18) - 11 x 15 FBGA 1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC DQb DQb DQb DQb DPb NC MODE 2 A A NC DQb DQb DQb DQb VSS NC NC NC NC NC 72M 36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A 11 A 144M DPa DQa DQa DQa DQa ZZ NC NC NC NC NC A A Document #: 38-05240 Rev. *A Page 5 of 33 PRELIMINARY Pin Definitions Name A0 A1 A BWa BWb BWc BWd GW I/O InputSynchronous InputSynchronous Description CY7C1380CV25 CY7C1382CV25 Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. InputSynchronous InputSynchronous Input-Clock Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. (TQFP Only) Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. (TQFP Only) Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O p

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CY7C1382CV25

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