128Kx36 Flow-Through SRAM

www.DataSheet4U.com CY7C1351 128Kx36 Flow-Through SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices IDT71V547, MT55L128L36F, and MCM63Z737 • Supports 66-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for Flow-Through operation • Byte Write capability • 128K x 36 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 11.0 ns (for 66-MHz device) — 12.0 ns (for 50-MHz device) • • • • • — 14.0 ns (for 40-MHz device) Clock Enable (CEN) pin to suspend operation Synchronous self-timed writes Asynchronous Output Enable JEDEC-standard 100 TQFP package Burst Capability—linear or interleaved burst order Low standby power Functional Description The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1351 is pin/functionally compatible to ZBT SRAMs IDT71V547, MT55L128L36F, and MCM63Z737. All synchronous inputs pass through input registers controlled by the rising edge of the clock.The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 11.0 ns (66-MHz device). Write operations are controlled by the four Byte Write Select (BWS[3:0]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Logic Block Diagram CLK CE ADV/LD A[16:0] CEN CE1 CE2 CE3 WE BWS [3:0] Mode 17 CONTROL and WRITE LOGIC 17 128KX36 MEMORY ARRAY 36 DQ[31:0] DP[3:0] D Data-In REG. Q 36 36 OE . Selection Guide 7C1351-66 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Commercial Commercial 11.0 250 mA 5 mA 7C1351-50 12.0 200 mA 5 mA 7C1351-40 14.0 175 mA 5 mA NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 August 9, 1999 CY7C1351 Pin Configuration 100-Pin TQFP ADV/LD BWS3 BWS2 BWS1 BWS0 CE1 CE2 CE3 VDD VSS CEN CLK WE OE NC A6 A7 NC A8 82 A9 81 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 DP2 DQ16 DQ17 VDDQ VSS DQ18 DQ19 DQ20 DQ21 VSS VDDQ DQ22 DQ23 VSS VDD VDD VSS DQ24 DQ25 VDDQ VSS DQ26 DQ27 DQ28 DQ29 VSS VDDQ DQ30 DQ31 DP3 100 83 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 80 79 78 77 76 75 74 73 72 71 70 DP1 DQ15 DQ14 VDDQ VSS DQ13 DQ12 DQ11 DQ10 VSS VDDQ DQ9 DQ8 VSS VSS VDD VSS DQ7 DQ6 VDDQ VSS DQ5 DQ4 DQ3 DQ2 VSS VDDQ DQ1 DQ0 DP0 CY7C1351 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 A16 DNU DNU A5 A4 A3 A2 A1 A0 A11 A12 A13 MODE VSS VDD DNU 2 DNU A10 A14 A15 CY7C1351 Pin Definitions Pin Number 50–44, 81–82, 99, 100, 32–37 96–93 Name A[16:0] I/O InputSynchronous InputSynchronous Description Address Inputs used to select one of the 133,072 address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWS0 controls DQ[7:0] and DP 0, BWS1 controls DQ [15:8] and DP1, BWS 2 controls DQ[23:16] and DP2, BWS0 controls DQ[31:24] and DP3. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A [16:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ[31:0] are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DP0 is controlled by BWS0, DP1 is controlled by BWS1, DP2 is controlled by BWS 2, and DP3 is controlled by BWS3. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. Ground for the device. Should be connected to ground of the system. BWS[3:0] 88 85 WE ADV/LD InputSynchronous InputSynchronous 89 98 97 92 86 CLK CE1 CE2 CE3 OE Input-Clock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous 87 CEN InputSynchronous 29–28, DQ[31:0] 25–22, 19–18, 13–12, 9–6, 3–2, 79–78, 75–72, 69–68, 63–62, 59–56, 53–52 1, 30, 51, 80 DP[3:0] I/OSynchronous I/OSynchronous Input Strap pin 31 MODE 15, 16, 41, 65, 91 VDD Power Supply I/O Power Supply Ground 4, 11, 20, 27, VDDQ 54, 61, 70, 77 5, 10, 14, 17, VSS 21, 26, 40, 60, 64, 66–67, 55, 71, 76, 90 3 CY7C1351 Pin Definitions (continued) Pin Number 83, 84 Name NC I/O Description No Connects. Reserved for address inputs for depth expansion. Pins 83 and 84 will be used for 256K and 512K depths respectively. Do Not Use pins. These pins should be left floating or tied to VSS. input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to A0–A16 is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ [31:0] and DP [3:0]. On the next clock rise the data presented to DQ [31:0] and DP [3:0] (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by BWS[3:0] signals. The CY7C1351 provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BWS[3:0]) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order t