Description
CY7C129*DV18/CY7C130*DV25 CY7C130*BV18/CY7C130*BV25/CY7C132*BV25 CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18 CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/ CY7C151*V18 /CY7C152*V18 Errata Revision: *C May 02, 2007 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for QDRI/DDRI/QDRII/DDRII. Details include trigger conditions, possible workarounds and silicon revision applicability. This document should be used to compare to the respective datasheet for the devices to fully describe the device functionality. Please www.DataSheet4U.com contact your local Cypress Sales Representative for availability of the fixed devices and any other questions. Devices Affected Density & Revision 9Mb - Ram9(90 nm) 9Mb - Ram9(90 nm) 18Mb - Ram9(90nm) Part Numbers CY7C130*DV25 CY7C129*DV18 CY7C130*BV18 CY7C130*BV25 CY7C132*BV25 CY7C131*BV18 CY7C132*BV18 CY7C139*BV18 CY7C191*BV18 CY7C141*AV18 CY7C142*AV18 CY7C151*V18 CY7C152*V18 Architecture QDRI/DDRI QDRII QDRI/DDRI 18Mb - Ram9(90nm) QDRII/DDRII 36Mb - Ram9(90nm) 72Mb -Ram9(90nm) Table 1. List of Affected devices QDRII/DDRII QDRII/DDRII Product Status All of the above densities and revisions are available in sample as well as production quantities. QDR/DDR DOFF Pin, Output Buffer and JTAG Issues Errata Summary The following table defines the issues and the fix status for the different devices which are affected. Item Issue Device Fix Status 1. DOFF pin is used for enabling/disabling the DLL circuitry within the SRAM. To enable the DLL circuitry, DOFF pin must be externally tied HIGH. The QDR-II/DDR-II devices have an internal pull down resistor of ~5K Ω . The value of the external pullup resistor should be 500 Ω or less in order to ensure DLL is enabled. 9Mb - “D” Rev - Ram9 18Mb - “B” Rev - Ram9 36Mb - “A” Rev - Ram9 72Mb - Ram9 QDR-II/DDR-II Devices The fix involved removing the internal pull-down resistor on the DOFF pin. The fix has been implemented on the new revision and is now available. Cypress Semiconductor Corporation Document #: 001-06217 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised:- May 02, 2007 Item Issue Device Fix Status 2. O/P Buffer enters a locked up undefined state after controls or clocks are left floating. No proper read/write access can be done on the device until a dummy read is performed. The EXTEST function in the JTAG test fails when input K clock is floating in the JTAG mode. 9Mb - “D” Rev - Ram9 18Mb - “B” Rev - Ram9 36Mb - “A” Rev - Ram9 72Mb - Ram9 QDR-I/DDR-I/ QDR-II/DDR-II Devices 9Mb - “D” Rev - Ram9 18Mb - “B” Rev - Ram9 36Mb - “A” Rev - Ram9 72Mb - Ram9 QDR-I/DDR-I/ QDR-II/DDR-II Devices The fix has been implemented on the new revision and is now available. 3. www.DataSheet4U.com The fix involved bypassing the ZQ circuitry in JTAG mode. This was done by overriding the ZQ circuitry by the JTAG signal. The fix has been implemented on the new revision and is now available. Table 2. Issue Definition and fix status for different devices 1. DOFF Pin Issue • ISSUE DEFINITION This issue involves the DLL not turning ON properly if a large resistor is used (eg:-10K Ω ) as an external pullup resistor to enable the DLL. If a 10K Ω or higher pullup resistor is used externally, the voltage on DOFF is not high enough to enable the DLL. • PARAMETERS AFFECTED The functionality of the device will be affected because of the DLL is not turning ON properly. When the DLL is enabled, all AC and DC parameters on the datasheet are met. • TRIGGER CONDITION(S) Having a 10K Ω or higher external pullup resistor for disabling the DOFF pin. • SCOPE OF IMPACT This issue will alter the normal functionality of the QDRII/DDRII devices when the DLL is disabled. • EXPLANATION OF ISSUE Figure 1 shows the DOFF pin circuit with an internal 5K Ω internal resistor. The fix planned is to disable the internal 5K Ω leaker. Figure 1. DOFF pin with the 5K Ω internal resistor • WORKAROUND Document #: 001-06217 Rev. *C Page 2 of 8 The workaround is to have a low value of external pullup resistor for the DOFF pin (recommended value is <500 Ω ). When DOFF pins from multiple QDR devices are connected through the same pull-up resistors on the board, it is recommended that this DOFF pin be directly connected to Vdd due to the lower effective resistance since the "leakers" are in parallel. Figure 2 shows the proposed workaround and the fix planned. www.DataSheet4U.com Figure 2. Proposed workaround with the 500 Ω external pullup • FIX STATUS Fix involved removing the internal pull-down resistor on the DOFF pin. The fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. The following table lists the devices affected, current revision and the new revision after the fix. Current Revision CY7C129*DV18 CY7C131*BV18 CY7C132*BV18 CY7C139*BV18 CY7C191*BV18 CY7C141*AV18 CY7C142*AV18 CY7C151*V18 CY7C152*V18 Table 3. List of Affected Devices and the new revison New Revision after the Fix CY7C129*EV18 CY7C131*CV18 CY7C132*CV18 CY7C139*CV18 CY7C191*CV18 CY7C141*BV18 CY7C142*BV18 CY7C151*AV18 CY7C152*AV18 2.Output Buffer Issue © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. • ISSUE DEFINITION This issue involves the output buffer entering an unidentified state when the input signals (only Control signals or Clocks) are floating during reset or initialization of the memory controller after power up. • PARAMETERS AFFECTED No timing parameters are affected. The device may drive the outputs even though the read operation is not enabled. A dummy read is performed to clear this condition. • TRIGGER CONDITION(S) Input signals(namely RPS# for QDR-I/QDRII , WE# and LD# for DDR-I/DDRII) or Clocks (K/K# and/or C/C#) are floating during reset or initialization of the memory controller after power up. • SCOPE OF IMPACT This issue will jeopardize any number of writes or reads which take place after the controls or clock are left floating. This can occur anywhere in the SRAM access ( all the way from power up of the memory device to www.DataSheet4U.com transitions taking place for read/write accesses to the memory device) if the above trigger conditions are met. • EXPLANATION OF ISSUE Figure 3 shows the output register Reset circuit with an SR Latch circled. This latch has two inputs with one of them coming from some logic affected by the clock and RPS#(QDR) or WE# and LD#(DDR).The issue happens when clocks are glitching/toggling with controls floating. This will cause the SR latch to be taken into an unidentified state. The SR Latch will need to be reset by a dummy read operation if this happens. SR LATCH Figure 3. Output Register Reset Circuit • WORKAROUND This is viable only if the customer has the trigger conditions met during reset or initialization of the memory controller after power up. In order for the workaround to perform properly, Cypress recommends the insertion of a minimum of 16 “dummy” READ operations to every SRAM device on the board prior to writing any meaningful data into the SRAM. After this one “dummy” READ operation, the device will perform properly. “Dummy” READ is defined as a read operation to the device that is not meant to retrieve required data. The “dummy” READ can be to any address location in the SRAM. Refer to Figure 4 for the dummy read implementation. Document #: 001-06217 Rev. *C Page 4 of 8 In systems where multiple SRAMs with multiple RPS# lines are used, a dummy read operation will have to be performed on every SRAM on the board. Below is an example sequence of events that can be performed before valid access can be performed on the SRAM. 1) Initialize the Memory Controller 2) Assert RPS# Low for each of the memory devices Note: For all devices with x9 bus configuration, the following sequence needs to be performed: 1) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 low respectively and perform dummy read. 2) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 high respectively and perform dummy read. www.DataSheet4U.com If the customer has the trigger conditions met during normal access to the memory then there is no workaround at this point. K /K QDRII Operation /RPS Address A DataOut (Q) C Q(A) E Q(A+1) Q(C) Q(C+1) G Q(E) Q(E+1) WE# Address DataOut (Q) Dummy Read DDRII Operation A C DQ(A) E DQ (A+1) DQ(C) DQ (C+1) G DQ DQ(E) (E+1) Figure 4. Dummy Read Implementation • FIX STATUS The fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. Please refer to Table 4 for the list of devices affected, current revision and the new revision after the fix. 3. JTAG Mode Issue • ISSUE DEFINITION If the input clock (K Clock) is left floating when the device is in JTAG mode, spurious high frequency noise on this input can be interpreted by the device as valid clocks. This could cause the impedance matchi

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