Description
www.DataSheet4U.com CY7C1298F 1-Mbit (64K x 18) Pipelined DCD Sync SRAM Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K × 18-bit common I/O architecture • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 3.5ns (for 166-MHz device) — 4.0ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous Output Enable • JEDEC-standard 100-pin TQFP package and pinout • “ZZ” Sleep Mode option Functional Description[1] The CY7C1298F SRAM integrates 65,536x18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance. The CY7C1298F operates from a +3.3V core power supply while all outputs operate with a +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 166 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 3.5 240 40 133 MHz 4.0 225 40 Unit ns mA mA Shaded areas contain advance information. Please contact your local CYpress sales representative for availability of these parts. Note: 1. . For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05417 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 7, 2004 CY7C1298F Functional Block Diagram—64Kx18 A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK Q1 BURST COUNTER AND LOGIC CLR Q0 ADSC ADSP DQB, DQPB BYTE WRITE REGISTER DQA , DQPA BYTE WRITE REGISTER ENABLE REGISTER DQB , DQPB BYTE WRITE DRIVER DQA, DQPA BYTE WRITE DRIVER MEMORY ARRAY SENSE AMPS BWB OUTPUT REGISTERS OUTPUT BUFFERS E DQs, DQPA DQPB BWA BWE GW CE1 CE2 CE3 OE PIPELINED ENABLE INPUT REGISTERS ZZ SLEEP CONTROL Document #: 38-05417 Rev. *A Page 2 of 15 CY7C1298F Pin Configurations 100-pin TQFP Top View VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A CY7C1298F (64K x 18) A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC MODE A A A A A1 A0 NC NC VSS VDD NC NC Document #: 38-05417 Rev. *A A A A A NC NC A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 15 CY7C1298F Pin Descriptions Pin A0, A1, A TQFP Type Description 37,36,32,33 InputAddress Inputs used to select one of the 64K address locations. Sampled at 34,35,44,45, Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 46,47,48,80, are sampled active. A[1:0] are fed to the two-bit counter. 81,82,99,100 93,94 88 InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes Synchronous to the SRAM. Sampled on the rising edge of CLK. InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge Synchronous of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE). InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This Synchronous signal must be asserted LOW to conduct a byte write. InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. BW[A:B] GW BWE CLK CE1 CE2 CE3 OE 87 89 98 InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE1 and CE3 to select/deselect the device. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE1 and CE2 to select/deselect the device. InputOutput Enable, asynchronous input, active LOW. Controls the direction of the Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. InputAdvance Input signal, sampled on the rising edge of CLK, active LOW. When Synchronous asserted, it automatically increments the address in a burst cycle. InputAddress Strobe from Processor, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. InputAddress Strobe from Controller, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a three-state condition. Power Supply Power supply inputs to the core of the device. Ground I/O Power Supply I/O Ground Ground for the core of the device. Power supply for the I/O circuitry. 97 92 86 ADV ADSP 83 84 ADSC 85 ZZ 64 DQs DQP[A:B] 8,9,12,13, 18,19,22, 23,24,58, 59,62,63, 68,69,72, 73,74 15,41,65, 91 17,40,67, 90 4,11,20,27, 54,61,70, 77 5,10,21,26, 55,60,71, 76 VDD VSS VDDQ VSSQ Ground for the I/O circuitry. Document #: 38-05417 Rev. *A Page 4 of 15 CY7C1298F Pin Descriptions (continued) Pin MODE 31 TQFP Type InputStatic Description Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not internally connected to the die. NC 1,2,3,6,7,14, 16,25,28,29, 30,38,39,42, 43,49,50,51, 52,53,56,57, 66,75,78,79, 95,96 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1298F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous Chip Selects CE1, CE2, CE3 and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock r

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