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CY7C1292DV18 CY7C1294DV18
9-Mbit QDR- II™ SRAM 2-Word Burst Architecture
Features
• Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth • 2-Word Burst on all accesses • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 500 MHz) @ 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • Available in x 18 and x 36 configurations • Full data coherency, providing most current data • Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD • Available in 165-ball FBGA package (13 x 15 x 1.4 mm) • Offered in both lead-free and non-lead free packages • Variable drive HSTL output buffers • JTAG 1149.1 compatible test access port • Delay Lock Loop (DLL) for accurate data placement
Functional Description
The CY7C1292DV18 and CY7C1294DV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with two 18-bit words (CY7C1292DV18) or 36-bit words (CY7C1294DV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.” Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1292DV18 – 512K x 18 CY7C1294DV18 – 256K x 36
Selection Guide
250 MHz Maximum Operating Frequency Maximum Operating Current 250 600 200 MHz 200 550 167 MHz 167 500 Unit MHz mA
Cypress Semiconductor Corporation Document #: 001-00350 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709 • 408-943-2600 Revised July 20, 2006
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CY7C1292DV18 CY7C1294DV18
Logic Block Diagram (CY7C1292DV18)
D[17:0] 18 Write Reg
Write Add. Decode
A(17:0)
18
Read Add. Decode
Address Register
Write Reg 256K x 18 Array
Address Register
18
A(17:0)
256K x 18 Array
K K
CLK Gen.
Control Logic
RPS C C
DOFF
Read Data Reg. 36 Control Logic 18 Reg. 18 Reg. 18 Reg.
CQ CQ
VREF WPS BWS[1:0]
18 18 Q[17:0]
Logic Block Diagram (CY7C1294DV18)
D[35:0] 36 Write Reg
Write Add. Decode
A(16:0)
17
Read Add. Decode
Address Register
Write Reg 128K x 36 Array
Address Register
17
A(16:0)
128K x 36 Array
K K
CLK Gen.
Control Logic
RPS C C
DOFF
Read Data Reg. 72 Control Logic 36 Reg. 36 Reg. 36 Reg.
CQ CQ
VREF WPS BWS[3:0]
36
36
Q[35:0]
Document #: 001-00350 Rev. *A
Page 2 of 23
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CY7C1292DV18 CY7C1294DV18
Pin Configurations 165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1292DV18 (512K x 18)
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK
3
D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A
4
WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
NC/288M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
NC/18M NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
NC/72M NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS
11
CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
NC/144M NC/36M
CY7C1294DV18 (256K x 36)
1 A B C D E F G H J K L M N P R
CQ Q27 D27 D28 Q29 Q30 D30 DOFF D31 Q32 Q33 D33 D34 Q35 TDO
2
Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK
3
D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A
4
WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K NC/18M VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
10
11
CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
NC/288M NC/72M
NC/36M NC/144M D17 Q17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS
Document #: 001-00350 Rev. *A
Page 3 of 23
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CY7C1292DV18 CY7C1294DV18
Pin Definitions
Pin Name D[x:0] I/O Pin Description InputData input signals, sampled on the rising edge of K and K clocks during valid write Synchronous operations. CY7C1292DV18 - D[17:0] CY7C1294DV18 - D[35:0] InputWrite Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted Synchronous active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[x:0] to be ignored. InputByte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and K clocks Synchronous during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1292DV18 − BWS0 controls D[8:0], BWS1 controls D[17:9]. CY7C1294DV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. InputAddress Inputs. Sampled on the rising edge of the K (Read address) and K (Write address) Synchronous clocks during active Read and Write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of 256K x 18) for CY7C1292DV18 and 256K x 36 (2 arrays each of 128K x 36) for CY7C1294DV18. Therefore 18 address inputs for CY7C1292DV18 and 17 address inputs for CY7C1294DV18. These inputs are ignored when the appropriate port is deselected. OutputsData Output signals. These pins drive out the requested data during a Read operation. Valid Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q[x:0] are automatically tri-stated. CY7C1292DV18 − Q[17:0] CY7C1294DV18 − Q[35:0] InputRead Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers. Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. The rising edge of K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. CQ is referenced with respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. CQ is referenced with respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
WPS
BWS0, BWS1, BWS2, BWS3
A
Q[x:0]
RPS
C
C
Input
